This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM57L843: Clock Monitor Test

Part Number: RM57L843
Other Parts Discussed in Thread: TMS570LC4357

Hello,

I am trying to perform the Clock Monitor Test from the TI Safety Library on a RM57 / TMS570LC4357 and am not getting the expected results.

It is never getting the oscillator fail flag in the GBLSTAT register or the ESM. According to the CSDISSET and CSSTATUS, the oscillator is disabled. Does this test need to run prior to initializing any peripherals as the technical reference states that the clock will not be disabled until there are no active consumers.

Code:

void checkClockMonitor(void)
{
    uint32_t ghvsrc_bk;

    /* Enable clock monitor range detection circuitry */
    systemREG1->CLKTEST |= 0x03000000U;

    /* Backup register GHVSRC */
    ghvsrc_bk = systemREG1->GHVSRC;

    /* Switch all clock domains to HF LPO */
    systemREG1->GHVSRC = 0x05050005U;

    /* Disable oscillator to cause a oscillator fail */
    systemREG1->CSDISSET = 0x1U;

    /* Wait till oscillator fail flag is set */
    while((systemREG1->GBLSTAT & 0x1U) == 0U)
    {
    } /* Wait, Never gets passed this point */

    if((esmREG->SR1[0U] & 0x800U) != 0x800U)
    {
        health_policy(PLATFORM_ERROR, TEST_ERROR_CLOCK_MONITOR);
    }
    else
    {
        /* Clear ESM flag */
        esmREG->SR1[0U] = 0x800U;

        /* Disable clock monitor range detection circuitry */
        systemREG1->CLKTEST &= ~(0x03000000U);

        /* Enable oscillator */
        systemREG1->CSDISCLR = 0x1U;

        /* Wait until oscillator is enabled */
        /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
        while((systemREG1->CSVSTAT & 0x3U) == 0U)
        {
        } /* Wait */

        /* Clear oscillator fail flag and PLL slip flag if any*/
        systemREG1->GBLSTAT = 0x301U;

        /* Switch back all clock domains */
        systemREG1->GHVSRC = ghvsrc_bk;
    }
}

Thanks!

  • Hello Dimtri,

    Please also switch VCLKASRC (Peripheral asynchronous clock) to HF LPO (clock source 5), and switch RTI clock source (RCLKSRC) to HP LPO.

    systemREG1->CLKTEST |= 0x03000000U;

    systemREG1->GHVSRC = (uint32)((uint32)SYS_LPO_HIGH << 24U)

                          | (uint32)((uint32)SYS_LPO_HIGH << 16U)

                          | (uint32)((uint32)SYS_LPO_HIGH << 0U);

    systemREG1->VCLKASRC = (uint32)((uint32)SYS_LPO_HIGH << 0U);

    systemREG1->RCLKSRC &= ~0x0F;

    systemREG1->RCLKSRC |= SYS_LPO_HIGH;

    systemREG1->CSDISSET = 0x00000001U;

    while((systemREG1->CSDIS & 0x01U) != 0x01U) {;}

     

    Just tested ion RM46 launchpad, the bit 0 of systemREG1->GBLSTAT is set.

  • Thanks for the reply QJ,

    Still the same results. GBLSTAT bit 0 never goes high. Running on an RM57 I tried to change VCLKASRC VCLKA2S and VCLKACON1 as well, with no luck. RCLKSRC has some reserved bits that looked like a clock source as well that I tried to alter.

    Code:
    void checkClockMonitor(void)
    {
    uint32_t ghvsrc_bk;

    /* Enable clock monitor range detection circuitry */
    systemREG1->CLKTEST |= 0x03000000U;

    /* Backup register GHVSRC */
    ghvsrc_bk = systemREG1->GHVSRC;

    /* Switch all clock domains to HF LPO */
    systemREG1->GHVSRC = (uint32_t)((uint32_t)SYS_LPO_HIGH << 24U)

    | (uint32_t)((uint32_t)SYS_LPO_HIGH << 16U)

    | (uint32_t)((uint32_t)SYS_LPO_HIGH << 0U);

    /* switch RTI and Peripheral ASYNC clock source to LPO to HP LPO */
    systemREG1->VCLKASRC = (uint32_t)((uint32_t)SYS_LPO_HIGH << 8U)
    | (uint32_t)((uint32_t)SYS_LPO_HIGH << 0U);

    systemREG2->VCLKACON1 &= ~0xF000F;
    systemREG2->VCLKACON1 |= (uint32_t)((uint32_t)SYS_LPO_HIGH << 16U)
    | (uint32_t)((uint32_t)SYS_LPO_HIGH << 0U);

    systemREG1->RCLKSRC &= ~0xF000F;
    systemREG1->RCLKSRC |= (uint32_t)((uint32_t)SYS_LPO_HIGH << 16U)
    | (uint32_t)((uint32_t)SYS_LPO_HIGH << 0U);


    /* Disable oscillator to cause a oscillator fail */
    systemREG1->CSDISSET = 0x1U;

    /* Wait till oscillator fail flag is set */
    while((systemREG1->GBLSTAT & 0x1U) == 0U)
    {
    } /* Wait */

    if((esmREG->SR1[0U] & 0x800U) != 0x800U)
    {
    health_policy(PLATFORM_ERROR, TEST_ERROR_CLOCK_MONITOR);
    }
    else
    {
    /* Clear ESM flag */
    esmREG->SR1[0U] = 0x800U;

    /* Disable clock monitor range detection circuitry */
    systemREG1->CLKTEST &= ~(0x03000000U);

    /* Enable oscillator */
    systemREG1->CSDISCLR = 0x1U;

    /* Wait until oscillator is enabled */
    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
    while((systemREG1->CSVSTAT & 0x3U) == 0U)
    {
    } /* Wait */

    /* Clear oscillator fail flag and PLL slip flag if any*/
    systemREG1->GBLSTAT = 0x301U;

    /* Switch back all clock domains */
    systemREG1->GHVSRC = ghvsrc_bk;
    }
    }
  • Any update on this? Is this test available on rm57 / tms570lc4357?
  • Hi Dmitri,

    I need to do a test with the code above.
  • Hi Dmitri,

    Tested on RM57 launchpad, the bit 0 of GlbStat register is SET.

  • I cannot reproduce the results, here is my register state when I am stuck at GBLSTAT:

    *0xffffff00 *systemREG1 *0xffffff00
    0x0 SYSPC1 0x0
    0x4 SYSPC2 0x1
    0x8 SYSPC3 0x0
    0xc SYSPC4 0x0
    0x10 SYSPC5 0x0
    0x14 SYSPC6 0x0
    0x18 SYSPC7 0x0
    0x1c SYSPC8 0x0
    0x20 SYSPC9 0x1
    0x24 rsvd1 0x20
    0x28 rsvd2 0x0
    0x2c rsvd3 0x0
    0x30 CSDIS 0x8d
    0x34 CSDISSET 0x8d
    0x38 CSDISCLR 0x8d
    0x3c CDDIS 0x20
    0x40 CDDISSET 0x20
    0x44 CDDISCLR 0x20
    0x48 GHVSRC 0x5050005
    0x4c VCLKASRC 0x505
    0x50 RCLKSRC 0x1050105
    0x54 CSVSTAT 0xb8
    0x58 MSTGCR 0x205
    0x5c MINITGCR 0x5
    0x60 MSINENA 0x0
    0x64 MSTFAIL 0x0
    0x68 MSTCGSTAT 0x0
    0x6c MINISTAT 0x0
    0x70 PLLCTL1 0x40079500
    0x74 PLLCTL2 0x3fc0703d
    0x78 SYSPC10 0x0
    0x7c DIEIDL 0x1501f00c
    0x80 DIEIDH 0x802a83c
    0x84 rsvd4 0x0
    0x88 LPOMONCTL 0x100120e
    0x8c CLKTEST 0x30a0000
    0x90 DFTCTRLREG1 0x1105
    0x94 DFTCTRLREG2 0x5
    0x98 rsvd5 0x0
    0x9c rsvd6 0x0
    0xa0 GPREG1 0x0
    0xa4 rsvd7 0xdefa0005
    0xa8 rsvd8 0x0
    0xac rsvd9 0x0
    0xb0 SSIR1 0x0
    0xb4 SSIR2 0x0
    0xb8 SSIR3 0x0
    0xbc SSIR4 0x0
    0xc0 RAMGCR 0x50000
    0xc4 BMMCR1 0xa
    0xc8 rsvd10 0x0
    0xcc CPURSTCR 0x0
    0xd0 CLKCNTL 0x1010100
    0xd4 ECPCNTL 0x7
    0xd8 rsvd11 0x0
    0xdc DEVCR1 0xa
    0xe0 SYSECR 0x4000
    0xe4 SYSESR 0x0
    0xe8 SYSTASR 0x0
    0xec GBLSTAT 0x0
    0xf0 DEVID 0x8044ad0d
    0xf4 SSIVEC 0x0
    0xf8 SSIF 0x0

    *0xffffe100 *systemREG2 *0xffffe100
    0x0 PLLCTL3 0x79500
    0x4 rsvd1 0x0
    0x8 STCCLKDIV 0x0
    0xc rsvd2 {0x5,0x505,0x0,0x0,0x0,0xb}
    0x24 ECPCNTL 0x7
    0x28 ECPCNTL1 0x50000000
    0x2c rsvd3 {0x0,0x0,0x0,0x0}
    0x3c CLK2CNTRL 0x101
    0x40 VCLKACON1 0x50005
    0x44 rsvd4 {0x1,0x1090109,0x0,0x1090109}
    0x54 HCLKCNTL 0x1
    0x58 rsvd5 {0x0,0x0,0x0,0x0,0x0,0x0}
    0x70 CLKSLIP 0x5
    0x74 rsvd6 0x5
    0x78 IP1ECCERREN 0x5050505
    0x7c rsvd7 {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}
    0xec EFC_CTLEN 0x5
    0xf0 DIEIDL_REG0 0x1501f00c
    0xf4 DIEIDH_REG1 0x802a83c
    0xf8 DIEIDL_REG2 0x0
    0xfc DIEIDH_REG3 0x39aa0002
  • I was able to run this on an XRM57 HDK, but the same binary does not work on a production RM57 board.

    The only difference seems to be the Device ID registers as far as sysREG1 and sysREG2 are concerned.

    Any other registers I should check, or is this a chip errata / hardware issue?

    Thanks
  • Hi Dmitri,

    I don't think it is a hardware issue. What board are you using?

    Can you please disable the cache? If you enable the cache, the memory browser may not update immediately?

  • The test passes on a RM57 HDK ASSY 419782 REV-E the chip is labeled as XRM57 L843ZWTT YFA-49ASEXW
    The test fails (gets stuck waiting on GBLSTAT) on a custom PCB based based off the HDK, Chip is labeled RM57 LB843BZWTT TFB-64C38HW.

    Both running the same binary.
  • Also tried to run on a PRM57 L843ZWTT YFB-55AV86W. Stuck at GBLSTAT.
  • I believe it has to do with out PCB hardware design. Ran this on an HDK board (with a socket for replaceable chip) with same TMS570LC4357BZWTQQ1 model chip installed with the HDK hardware passing the test and the custom PCB failing the test.
  • Could this be caused by not wiring pin L2 (Kelvin_GND) and L1 (OSCOUT) as recommended in the data sheet www.ti.com/.../rm57l843.pdf section 6.6.1.1 Main Oscillator?
  • Hi Dmitri,

    If you use an external crystal as clock source, the external crystal load capacitors should be tied back to kelvin_GND.Kelvin_GND is not intended to be shorted to other GND lines externally.

    It might be the cause, but I am not sure.
  • QJ, so if we use an external MEMS oscillator, should Kelvin_GND be left floating or should it connect to the same board ground as VSS on the part?  The manual is highly unclear about what to do.  It suggests that Kelvin_GND be left floating if a non-crystal MEMS oscillator is connected there.  What is the recommended solution?

    Best,

    Josh Karch

  • QJ please also note that Chuck Davenport provides different guidance about grounding KELVIN_GND to common ground when an external clock source (AKA MEMS Oscillator with 3.3V signal) is used.  The issue is oscillator failure detection is not working now with KELVIN_GND not connected with an external MEMS oscillator.

    Best

    Josh Karch

  • Hi Josh,

    yes, if you use external clock source which is connected to OSCIN, tie the kelvin_GND to the common ground of the PCB.