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Problem sending SPI bit stream

Mark Feldman
Prodigy 60 points
Other Parts Discussed in Thread: MSP430G2231

I'm trying to use the MSP430G2231 to send a continuous, unbroken stream of bits via SPI. My strategy is to use the 16-bit shift register, always keep USICNT > 0 and set the 8 bits of USISRL at exactly the right moment before they get shifted into USISRH and then out. My set-up code and first part of my main loop look like this:

SetupUSI    bis.b #USIPE6+USIPE5+USIMST+USIOE,&USICTL0
            mov.b #USIDIV_0+USISSEL_2, &USICKCTL		; = SMCLK
            bic.b #USISWRST, &USICTL0				; Enable USI
            mov.b #0AAh, R4
            mov.b #USI16B + 1Fh, R5
           
Mainloop    mov.b R5, &USICNT
            mov.b R4, &USISRL
            nop
            nop
            nop
            nop
            nop
            mov.b R4, &USISRL
            ... long delay here...

No matter what I try though I can't get the timing exactly right. Looking at the waveform on an oscilloscope it looks like the SPI shift counter stalls for a cycle whenever a value is written to USISRL, is that correct? And if so is there a way I can turn it off? Or is there a better way to do what I'm trying to do?

(Edited once to correct spelling mistakes)

  • 0
    Guru 12160 points

    Hi Mark,

    I've never used the USI, so hopefully somebody will still comment on that part of it.

    However, the best way to do what you are trying to do is with the USCI, which is in other 2xx MCUs and all the 5xx MCUs.  It is double buffered so it will keep the clock ticking in phase through byte transitions.

    If you do end up picking another MCU, then you might as well get one with DMA too.  The DMA controller can effectively give you queued SPI (aka FIFO SPI) which is really helpful if you want high bit rates or if your application has other things going on.

    Just curious, what are the rates of MCLK and SMCLK?

    Jeff

  • 0 in reply to Jeff Tenney
    Prodigy 60 points

    Jeff: I'm trying to generate a TV signal so I need to to run SMCLK at 16MHz, although the behavior I'm seeing appears to be the same regardless of clock speed. DMA is too slow unfortunately...2 clocks per bit.

    I haven't used USCI before, are you sure it can maintain maximum though-put without any stalls between characters?

    Cheers,

    Mark

     

  • 0 in reply to Mark Feldman
    Guru 12160 points

    Mark,

    I don't know anything about TV signals.  Is there much computation involved in generating the bit stream?  Will you have enough MCLKs per SCLK to generate each bit?  Or is your bitstream static?

    Anyway, yes I am sure that the USCI can generate a steady bitstream with no stalls and staying properly in phase.  You just have to keep the TXBUF register stuffed.  Once it becomes empty, you have 8 clock cycles to get it stuffed again or else there will be a stall.  That's where the DMA controller comes in.  It will stuff the TXBUF for you (not control the pin directly--sorry if I wasn't clear before).  That would leave 6 of every 8 clocks for the CPU to work (assuming MCLK = SMCLK) with no worry of being late writing to the TXBUF (due to ISR interference or other tasks). 

    Jeff

  • 0 in reply to Jeff Tenney
    Prodigy 60 points

    I just checked the data sheet for the MSP430G2231 and it doesn't look like the chip supports UCSI. The MSP430x2xx User Guide has a section on it but says to check the data sheet of the specific device you're using, and the MSP430G2231 data sheet talks all about USI but no mention of UCSI. Nothing in the device header file either :( Which is a real shame because it would have fit the bill perfectly.

    Oh well, back to the original problem then I guess.

     

  • 0 in reply to Mark Feldman
    Guru 227245 points

    In the thread about the new LaunchPad design, the reason for the new design (and the thread) was the fact that a new upcoming G chip will have a hardware UART. It's just a guess but this seems to indicate that this chip will have an USCI module in addition or instead of the USI.
    The USCI does not support variable-length SPI transfers (only 8 bit), but has hardware USART and two SPI units in addition of the I2C (while only two of the four can be used at the same time).

     

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