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LX4F232H5QDFIGA1 ADCTSSEL register

SourceTwo
Expert 2355 points

Hello,

I wanted to share a discovery (probable errata) I made with regards to triggering ADC Module0 from PWM Module1.  From page 871 of the March 08, 2012 data sheet:

The ADCTSSEL register specifies which PWM module is selected with the EMn bit field in the ADC Event Multiplexer Select (ADCEMUX) register. The register resets to 0x0000.0000, which selects PWM module 0 for all generators.

This March 08, 2012 data sheet revised the bit field placement in ADCTSSEL from its predecessor, but is still does not seem to match the functioning of the device.  In my test code, SS1 is to be triggered from PWM Module 1.  According to the data sheet, ADCTSSEL = 0x00001000 would patch the trigger from PWM Module 1 to the  SS1 selection field in ADCEMUX.  This does not work, as SS1 continues to be triggered by PWM Module0.  After trying various bit positions, I found that ADCTSSEL = 0x00100000 works (directs PWM Module1 to SS1).  Note - this bit positioning _should_ affect the SS2 trigger mapping, but actually acts on SS1's trigger mapping.

TI: Can you please research and comment?  Either there is a device/documentation problem or I am severely misreading the datasheet.  Also, will this affect revision A3?  Will the Driver Library eventually include support for ADCTSSEL?

Thank you!

Regards,

Dave

 

 

  • 0
    Guru 117855 points

    Hello SourceTwo (nicely understated)

    This (or extremely close) has been noted/reported & acknowledged by TI.  http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/t/158612.aspx

    Would you be good enough to review - comment upon suitability of TI "fix?"   Regards...

  • 0 in reply to cb1_mobile
    Expert 2355 points

    Hi CB1,

    Wow - I mist apologize for missing (forgetting?) this older post.  It certainly is the same problem!

    With regards to TI's suggestion: yes the fields are shifted by four.  If I write 0xFFFFFFFF to the register (in uVision 4.50), it reverts to 0x30303030, thereby revealing the "writable bits".  However, there is more afoot:  to trigger SS1 from PWM1, I must set the bit in the field documented for SS2.  Presuming the ADCTSSEL register's 4 fields of bits are intended to increment from low to high ( SS0 to SS3) , this is probably an errata.  With luck, the full functionality is available if the documentation and Stellarisware macros are updated, but it is possible there is no way to remap the PWM Module 1 to trigger SS2.  If TI has a look at the silicon design source, they should be able to see what's up.

    A personal question: you have a strong and well appreciated presence on this forum - how do you manage it?  My guess is during flight time?

    Regards,

    Dave

  • 0 in reply to SourceTwo
    Guru 117855 points

    Hi SourceTwo/Dave,

    Apology totally unsought/needed - your finding adds to "body of knowledge."

    May I repay your kindness - you too are strong, helpful, well appreciated - see your valued posts often.  Have both friends & working colleagues @ TI (& other semi.)   Firm/I received great kindness years back - nice to be able to repay.  You got it - mix of small twin (club) & commercial - many clients - much "hurry up & wait" - ideal if I stick to few areas I know & poster is coherent/has laid some ground-work....  U.S. midwest cuts flight-time - extends client reach - most prize personal touch/feel...

    In many cases - have list of sound concepts/ideas - have yet to attempt/verify - then "eureka" post lands - often "beg" questing poster to "implement the plan."  Benefits poster, myself/firm, and forum - pretty good leverage of resource I'd say...  (and w/"enlightened' corp reward of mugs/T-shirts - sellers of olde Manhattan isle now appear "not so" dumb. {or they are now among bargaining equals...}) 

    The SourceTwo detail/comments on ADCTSSEL illustrates nicely - your findings have enhanced "body of knowledge," - benefitting many.  Olde cb1 served as simple facilitator...  Thank you & stay well...