Android ICS on Custom board LCD Issue

Hi Haran,

As per my discussions with DSS R & D team, following are the suggestions for your above queries.

1. HDMI should be supporting resolutions up to 1080p. Ensure that the HDMI driver clock source is selected as PRCM source. If not it can lead to SYNC LOST.

2. High resolutions 1920 x 1200 do have impact on the performance as there is lot of bandwidth requirements for OMAP4460. But we do have OMAP4470 based tablet device with 1920 x 1200 support with no impact on performance as it allows higher L3 frequency along with ability to prioritize the DSS when required among L3 initiators.

3. GFX_FIFO_UNDERFLOW is a known issue due to limited size of GFX pipeline internal buffers which is not sufficient for resolutions such as 1080p & 1920 x 1200.

To address this issue, you can have simple fix by swapping the internal buffers of Writeback Pipeline and GFX pipeline as Writeback pipeline can suffice its needs with smaller internal buffers.

This can be achieved by setting the register bits of DISPC_GLOBAL_BUFFER accordingly at the probe time. Please refer to the OMAP4460 TRM for details on this register.

Default reset values for GFX TOP and BOTTOM internal buffers is 0x0 and for Writeback TOP and BOTTOM internal buffers is 0x4. Need to swap these values in the above register. In the default releases from TI, we do not modify this register as we only test with panels less than 1080p resolution.

If you are not planning to use Writeback pipeline, then you can set even Writeback TOP and Bottom internal buffers as 0x0 so that they get assigned to GFX pipeline.

FYI, GFX pipeline internal FIFO Size = 0x500 * 16 & for VID1, VID2, VID3 & Writeback Pipelines FIFO Size = 0x800 * 16.

In addition to the above change, ensure that the fifo size is initialized properly for the GFX pipeline in the following API of dispc.c ($KERNELDIR/drivers/video/omap2/dss)

static void dispc_read_plane_fifo_sizes(void)
{
        u32 size;
        int plane;
        u8 start, end;

        dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);

        for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
                size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
                        start, end);
                //dispc.fifo_size[plane] = size;

                if(plane == 0) {

                    // if you have swapped the internal buffers of writeback and gfx pipeline by modifying the DISPC_GLOBAL_BUFFER register

                   dispc.fifo_size[plane] = (0x800 * 16);

                                      (OR)

                    // if you have assigned even the internal buffers of writeback to gfx pipeline by modifying the DISPC_GLOBAL_BUFFER register

                   dispc.fifo_size[plane] = ((0x800 + 0x500) * 16);

                }

                 else

                    dispc.fifo_size[plane] = size;

        }
}

The above changes would ensure GFX_FIFO_UNDERFLOW will not happen.

In addition, you have to ensure that the PRCM clock source is chosen for the LCD panel of yours since it has 1920x1200 resolution.

Please let us know if you need ffurther clarifications.

Thanks & Best Regards,

Venkat