10G Ethernet example

The u-boot does not support 10GbE. The driver has not been implemented yet. Linux will support

http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring

Thanks;

I know, I wrote it as above.

I asked that do you have 10G example ? 

odc,
The 10Gig Ethernet Driver provides its API to the NETCP driver by registering itself to an instance of the NETCP driver during kernel initialization.
The 10Gig Ethernet Driver code can be found in files keystone_xgess.c, keystone_xgepcsr.c and keystone_xgemdio.c in directory drivers/net/ethernet/ti/.
In addition that, I have answered on your previous E2E thread,
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/391914

Thanks for your reply

But we use Sys/Bios and our uboot version doesnt provide Xge.

On the other hand, when we check PCSR module from datasheet, TBD(to be decided) is written to all register description. So we cant create any desing because we dont understand anything from register. 

I suggest you, Either supply example to your Keystone consumer or write datasheet properly and clearly.

Also we create SR to our TI providers but reply doesnt come already we are waiting our special providers. 

Thanks

Hi,You check the latest version of MCSDK3.x, it have 10Ge CSL drive support.
Refer the "csl_serdes_10ge" file in the mcsdk.
And also find the files at PDK: ti\pdk_keystone2_3_01_01_04\packages\ti\csl\src\ip\serdes_sb\V0\

Thanks for reply

I found and applied it.

But major problem is in 10Gbe ethernet module(Submodule, ALE, MAC, PCSR, CPSW) init.

There is no any example and documentation isnt enough for set XgE

 

Odc,
Yes, We agree for not provide the example and less documentation. This will be resolve in the upcoming release. If possible,You can share the modified code for 10GbE. This will be useful for the future readers.

Yes possible, may be someone find wrong side of my code

#define XGE_CFG_BASE_ADDR 0x2F00000
#define SUB_CTRL (XGE_CFG_BASE_ADDR + 0xC)
#define SOFT_RESET_PORT1 (XGE_CFG_BASE_ADDR + 0x0104)
#define SGMII_CONTROL_PORT1 (XGE_CFG_BASE_ADDR + 0x0110)
#define SOFT_RESET_PORT2 (XGE_CFG_BASE_ADDR + 0x0204)
#define SGMII_CONTROL_PORT2 (XGE_CFG_BASE_ADDR + 0x0210)
#define PCSR_CTRL_PORT_1 (XGE_CFG_BASE_ADDR + 0x600 + 0x24)
#define PCSR_CTRL_PORT_2 (XGE_CFG_BASE_ADDR + 0x680 + 0x24)
#define CPSW_TX_START_WDS (XGE_CFG_BASE_ADDR + 0x1020)
#define CPSW_CTRL_REG (XGE_CFG_BASE_ADDR + 0x01004)
#define CPSW_STAT_PORT_EN_REG (XGE_CFG_BASE_ADDR + 0x0100C)
#define CPSW_FLOW_CTRL_REG (XGE_CFG_BASE_ADDR + 0x01024)
#define MAC1_CTRL_REG (XGE_CFG_BASE_ADDR + 0x01404)
#define MAC2_CTRL_REG (XGE_CFG_BASE_ADDR + 0x01444)
#define ALE_CONTROL_REG (XGE_CFG_BASE_ADDR + 0x01708)
#define ALE_PORTCTL0_REG (XGE_CFG_BASE_ADDR + 0x01740)
#define ALE_PORTCTL1_REG (XGE_CFG_BASE_ADDR + 0x01744)
#define ALE_PORTCTL2_REG (XGE_CFG_BASE_ADDR + 0x01748)
#define ALE_TBLCTL_REG (XGE_CFG_BASE_ADDR + 0x01720)
#define ALE_ENTRY0_REG (XGE_CFG_BASE_ADDR + 0x0173C)
#define ALE_ENTRY1_REG (XGE_CFG_BASE_ADDR + 0x01740)
#define ALE_ENTRY2_REG (XGE_CFG_BASE_ADDR + 0x01744)


void XGbeSerdesSetup(){


CSL_SERDES_REF_CLOCK refClock;
CSL_SERDES_LINK_RATE linkRate;
Uint32 baseAddr;
CSL_SERDES_RESULT csl_retval;
Uint32 i;
CSL_SERDES_LANE_CTRL_RATE lane_rate;
CSL_SERDES_STATUS pllstat;
CSL_SERDES_LANE_ENABLE_STATUS lane_retval;

int val;
Uint32 lane_num;

csl_retval = CSL_10GeSerdesInit(CSL_XGE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_156p25M, CSL_SERDES_LINK_RATE_10p3125G);

if (csl_retval != 0)
{
printf ("Invalid XGE Serdes Init Params: %d\n", csl_retval);
}

for( lane_num = 0; lane_num<2; lane_num++)
CSL_10GeSerdesLaneConfig(CSL_XGE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_156p25M, CSL_SERDES_LINK_RATE_10p3125G, lane_num);

CSL_10GeSerdesComEnable(CSL_XGE_SERDES_CFG_REGS, CSL_SERDES_LINK_RATE_10p3125G);

for( lane_num = 0; lane_num<2; lane_num++){
CSL_10GeSerdesLaneEnable(CSL_XGE_SERDES_CFG_REGS, lane_num, CSL_SERDES_LINK_RATE_10p3125G, CSL_SERDES_LOOPBACK_DISABLED);

}

CSL_10GeSerdesPllEnable(CSL_XGE_SERDES_CFG_REGS, CSL_SERDES_LINK_RATE_10p3125G);

do
{
pllstat = CSL_10GeSerdesGetStatus(CSL_XGE_SERDES_CFG_REGS, 2);
}while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);

}


void CPSW_init(){

DEVICE_REG32_W(CPSW_CTRL_REG, 0x04);
DEVICE_REG32_W(CPSW_TX_START_WDS, 0x08);
DEVICE_REG32_W(CPSW_STAT_PORT_EN_REG, 0x7);
DEVICE_REG32_W(CPSW_FLOW_CTRL_REG, 0x7);
}


void ALE_init(){

DEVICE_REG32_W(ALE_CONTROL_REG, 0x80000002);
DEVICE_REG32_W(ALE_PORTCTL0_REG, 0x03);
DEVICE_REG32_W(ALE_PORTCTL1_REG, 0x03);
DEVICE_REG32_W(ALE_PORTCTL2_REG, 0x03);
/*DEVICE_REG32_W(ALE_TBLCTL_REG, 0x80000003);
DEVICE_REG32_W(ALE_ENTRY0_REG, 0x44332211);
DEVICE_REG32_W(ALE_ENTRY1_REG, 0x10006655);
DEVICE_REG32_W(ALE_ENTRY2_REG, 0xC0);*/



}



void PCSR_init(){
DEVICE_REG32_W(PCSR_CTRL_PORT_1, 0x2);
DEVICE_REG32_W(PCSR_CTRL_PORT_2, 0x2);
}


Uint32 Xgbe_powerup(){
CSL_PSC_disablePowerDomain(CSL_PSC_PD_XGE);

CSL_PSC_enablePowerDomain (CSL_PSC_PD_XGE);

/* Enable the clocks too for SRIO */
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_XGE, PSC_MODSTATE_ENABLE);

/* Start the state transition */
CSL_PSC_startStateTransition (CSL_PSC_PD_XGE);

/* Wait until the state transition process is completed. */
while (!CSL_PSC_isStateTransitionDone (CSL_PSC_LPSC_XGE));

/* Return SRIO PSC status */
if ((CSL_PSC_getPowerDomainState(CSL_PSC_PD_XGE) == PSC_PDSTATE_ON) &&
(CSL_PSC_getModuleState (CSL_PSC_LPSC_XGE) == PSC_MODSTATE_ENABLE))
{
/* SRIO ON. Ready for use */
return 0;
}
else
{
/* SRIO Power on failed. Return error */
return -1;
}

}


void MAC_init(){

DEVICE_REG32_W(MAC1_CTRL_REG, 0x2119);
DEVICE_REG32_W(MAC2_CTRL_REG, 0x2119);
}


void Xgbe_init(){
Xgbe_powerup();
XGbeSerdesSetup();
CPSW_init();
PCSR_init();
ALE_init();
DEVICE_REG32_W(SUB_CTRL, 0x3);
MAC_init();

}


main()
{
.
.
.
Xgbe_init();
.

ODC,Thanks for sharing the piece of 10GbE support code here.