Hello everyone
We had a SRIO environment, in which two K2H EVM connected with one SRIO switch. We measured the SRIO throughput by transmitting the Nwrite and Nread packets to DDR3 and L2 SRAM in 4 lanes mode. And then, we compared our result with TI. TI result comes from this document on page 30, link here. The comparison is showing below.
From it we can see that TI has higher throughput than our results. This is because we use the SRIO switch and the switch may reduce the SRIO performance. Second, in TI result, the SRIO performance on L2SRAM and DDR is almost same. (Those two lines are overlapped in the below figure.)However, in our result, SRIO has better performance on L2 SRAM than DDR. BTW, we use DDR3B on the K2H EVM, working at 1600MTS. The DSP cores run at 1.2GHz.
So I want to know how TI employee can make the SRIO throughput on DDR and L2 SRAM the same?
Thanks
Xining
TI result is based on the below Table.
