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AM5728: VIP usage as high speed FPGA interface

Steven Liu1
Expert 4505 points
Part Number: AM5728


Hi Team,

  My customer now designs a system which uses AM5728 working with FPGA. 

  The data flow is over 10MB/s, so they are considering using the AM5728's VIP port to receive data from the FPGA.

  However, the data is not the camera capture data, but the data arrays needs to be calculated by A15 or DSP.  

  So I'd like to know, whether we could support the "RAW data" dealing on the AM5728? In other words, the requirement would be the A15 could get the original data, without any compression, convert, from the VIP port,  so as to implement some algorithm based on it.   

  

  • 0
    TI__Guru**** 393215 points
    Hi,

    I will ask the factory team to comment. They will respond here.
  • 0
    TI__Mastermind 22946 points

    It is possible to use the FPGA to bring the data in RAW format through VIP IP interface. Things to keep in mind are –

     

    1. Data should be sent in discrete sync mode. One of the configuration you can choose to send data is as shown in section 9.4.5.19.7 of TRM - VSYNC and ACTIVID(2)

     

    1. No other internal processing blocks of VIP like scaling, format conversion, and color conversion etc should be used.

     

    1. The line length shouldn’t be greater than 8K bytes as that’s the size of VIP line buffer.

     

    1. There is no limitation on frame height by the VIP HW IP but VIP driver has size restriction of 2048x1536.

     

    1. VIP diver resolution restriction can be modified by changing the MAX_W and MAX_H macro values in driver/media/platform/ti-vpe/vip.c file. Note that VIP driver treats this restriction in pixel resolution and not in actual byte size. So for example, if each pixel size is 16 bit, then MAX_W can take maximum value of 4096 as the VIP IP line buffer width is limited to 8K bytes. If each pixel is 3 bytes, then the MAX_W cannot be 4K.  

     

    1. VIP doesn’t signal End of Frame till the time it sees signal for start of new frame and hence another VSYNC start signal is required to be sent from FPGA after completion of sending the data for current frame.

     

    1. RAW Bayer format can be used to bring the data in. VIP driver supports 8 bit RAW format capture but not 16 bit. Minor enhancement will be needed in vip.c file to add 16 bit raw capture support.