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AM3354: Ethernet RX/TX operation with CPPI DMA

schezow
Prodigy 180 points
Part Number: AM3354


Hi all,

I have read the description of Ethernet operation in the TRM document(spruh73p).

I understand that the AM335x EMAC module uses CPPI DMA and CPPI Buffer Descriptors to transmit Ethernet frames.

When TX7_HDP writes the address of the Tx Descriptors buffer, the packet is delivered.

When the RX Descriptors address is written to RX0_HDP, the packet is received.

Descriptors store the location of the actual packet, which is typically in the area of ​​the CPPI RAM.

When I write a value to the CPPI DMA interface, the EMAC module operates as an IP and writes the address to the TX / RX_CP regs.

I think using the CPPI DMA Descriptor directly to TX/RX ethernet packets, does not seem to require additional ISR.

Does the EMAC module need to generate a TX / RX_PULSE interrupt? Are there exist ISR for Packet RX / TX in the AM335x?

  • 0
    TI__Guru**** 393215 points
    Hi,

    What software are you using?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 180 points
    To Biser,

    Windows 10 64bit, CCS v7.3, pdk-rtos-am335x-4.2.0.9, ndk-2.26.0, XDS100-v3 JTAG

    Best Regards.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 180 points
    To Biser,

    When I started in CCS, I created a ti / rtos minimum project.

    I added my code before doing BIOS_Start ()

    No thread creation code was added.

    The Ethernet frame was sent / received by the register read function.

    Best Regards.
  • 0 in reply to schezow
    TI__Guru**** 393215 points
    Thanks. I have notified the RTOS team. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 43296 points
    Hi

    The 3 Port Switch Ethernet Subsystem generates four interrupt events including TX/RX pulse interrupt. The EMAC driver for AM335x is already available in PDK C:\ti\pdk_am335x_1_0_9\packages\ti\drv\emac, are you planning to optimize the driver or trying to understand the design?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Prodigy 180 points

    To Garrett.

    Thanks for your reply.

    My final goal is to create a minimal unit of code for sending and receiving packets at the low level.

    I have already seen some files in that location.

    In TRM document, 13.3.2.4 CPDMA In the RX and TX Interface description, the user operates as a DMA using the CPPI interface (EMAC Port 0).

    The packet processing does not work in the ISR in ARM but in the DMA controller in EMAC.

    After the operation of the DMA controller, the RX / TX_PULSE interrupt is passed to the ARM core.

    As a conclusion, does RX / TX_PULSE not affect packet transmission / reception process?

    If the user writes all of the packet information in the CPPI RAM and activates the DMA controller, does the ARM need TX / RX_Pulse processing?

  • 0 in reply to schezow
    TI__Mastermind 43296 points
    Hi schezow,

    It's true the packet is processed in CPDMA sub module.
    The TX/RX_Pulse interrupt assists host to properly receive and transmit packets without packet loss.
    If the user writes all of the packet information in the CPPI RAM and activates the DMA controller, the packet will be transmitted even without TX_Pulse processing, however if the user continuously writes in a burst before TX_Pulse occurs, the packet may be dropped. Similarly, without RX_Pulse, host will have to poll to check if any new packets.
    The recommended operation for packet transmission and receive is described in section 14.4 Software Operation that does include TX/RX interrupt.

    Regards,
    Garrett