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Original question:

[TDA4M] Test Description of UDMA datasheet

[TDA4M] When a DRU transfers data, "Multi CH DDR 1MB to DDR 1MB" is not faster than "1CH DDR 1MB to DDR 1MB" . Why?

Yongsig Do
Expert 1690 points


Hello

I have a couple of question related to previos thread.

In UDMA datasheeet,

this table was summarized.

1. Why doesn't it seem like "Multi CH DDR 1MB to DDR 1MB" is faster than "1CH DDR 1MB to DDR 1MB" ?

    The CPU Load is even high.

2. What parameters should I configure to use multi channels of DMA ? I can't find anything about multi channel configuration.

    Is it "uint32_t txChNum and rxChnum" of the Udma_Chobj to be configured to use multi-channel?

Best regards

Yongsig.

  • 0
    TI__Expert 4935 points

    1. The UDMA UT uses one task per UDMA channel to initiate and wait for DMA. Due to this task context switching is involved and also cache misses will be higher because of this. This is the reason for difference in performance number. In case of DRU, the DDR and CPU was already loaded. Hence we see marginal decrease in the performance due task switching overheads and cache misses. In case of UDMA, the DDR was not fully utilized with 1 CH and hence we see more performance while using multiple channels.

    2. To use multiple channel, you need to allocate multiple channel using Udma_chOpen function multiple times. You can refer to UDMA chaining example present in pdk/packages/ti/drv/udma/examples/udma_chaining_test folder