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LMV772-Q1: Deciding on the input voltage range wrt to I/P common mode voltage

Francis_93
Prodigy 130 points
Part Number: LMV772-Q1
Other Parts Discussed in Thread: LMV772

Tool/software:

I am using the opamp LMV772.

I have non-Inverting negative feedback opamp configuration with gain is 11.

The opamp I/P is connected to a voltage divider and the application is voltage sensing

I am also using the second opamp in the IC as a buffer for another application, and there also the +ve input is connected to a resistor divide, to sense voltage.

Supply is single rail with GND as 0V and Supply as 5V.

In the datasheet the common mode voltage is mentioned as 0V to 4.1V. So this means I can only give a maximum of 4.1V to the non inverting terminal?

  • +1
    Guru 319720 points

    Yes; the voltage at either input must stay at least 0.9 V below the positive supply.

  • 0 in reply to Clemens Ladisch
    Prodigy 130 points

    I have a series resistance of 20K between the voltage divider and opamp non inv terminal. During one surge voltage condition the voltage divider o/p be 50V. So in order to calculate the injection current I need to know how much voltage will be there at the opamp non inv input { ( Iinj= 50V-Vip_non)/20k}. If I assume the worst case, as non inv pin voltage as zero, the injection current during surge will be 2.5mA. But I want to get the realistic value for non inv pin voltage, to size the series resistance. How to get that?

  • 0 in reply to Francis_93
    TI__Guru**** 169146 points

    Hello Anoop,

    Is this what you were describing? What are the values for R1, R2 and what is the equation constants? ; VOUT = VIN * Gain + Offset

  • 0 in reply to Ron Michallick
    Prodigy 130 points

    The circuit is correct except the following changes

    1. Offset is not available. R5 left side is connected to GND.

    2. R5 value is 1k & R4 value is 10k

    3. R1 47k & R2 is 4.7k

  • +1 in reply to Francis_93
    Guru 319720 points

    When the top of R1 is at 50 V, the opamp's input pin sees about 4.5 V. This is outside the common-mode range, so the output is not guaranteed to be correct. But it is inside the absolute maximum ratings, so the device will not be damaged.

    As long as the voltage at the pin is not above 5 V, no current flows. When the voltage at the pin is above 5 V, a current flows through the clamping diode, but it is limited by R1 and R3.

    There are no diodes between the two input pins.

  • +1 in reply to Francis_93
    TI__Guru**** 169146 points

    Francis,

    R1 and R2 have gain of 1/11 and op amp has forward gain of 11. So VOUT = VIN for VIN [0V to 5V] 

    With 50V input, IN+ is 4.54V and IN- is 0.454V; with such a difference between input voltages VCM is a meaningless concept.

    IN- is valid voltage, IN+ is above but inside rails, so output should stay at 5V.

  • 0 in reply to Ron Michallick
    Prodigy 130 points

    In this circuit the input bias current & input offset voltage of the opamp plays a role?

    It is mentioned that the input bias current maximum mentioned as 250pA ( @ VCM=1V ). This current will flow into the opamp i/p pin or out of it?

    In case of R1 top side is not connected to a voltage source ( Ex : 50V surge ), The input bias current will create a voltage drop across R3 & R2 along with the input offset voltage right?

    How to calculate this?

    Also input bias current mentioned @ VCM=1V, so for this use case how much should I consider?

  • 0 in reply to Francis_93
    Guru 319720 points

    For CMOS opamps, the input bias current is somewhat random and could flow in either direction.

    The input bias current is so small that you can ususally ignore it (the voltage drop over the resistors would be < 1 µV); the offset voltage of up to 1 mV is much larger and will result in an error of up to ±11 mV at the output.

  • 0 in reply to Clemens Ladisch
    Prodigy 130 points

    Okey, But we need to understand in which direction the input bias current is flowing to decide whether the voltage drop due to input bias current to be added or subtracted from the opamp input voltage. What is the limitation for not knowing the direction of opamp input bias current?

  • 0 in reply to Francis_93
    TI__Guru**** 169146 points
    Francis_93 said:
    What is the limitation for not knowing the direction of opamp input bias current?

    You need to do two calculations, one for each possible current direction. 

  • 0 in reply to Francis_93
    Guru 319720 points

    The input bias current and the offset voltage are random and can go in either direction. The only way to adjust for them is to measure them for each chip (at a specific temperature).