AM62P-Q1: MIPI DSI D-PHY doesn't seem to be clocking.

Please ignore the "[ 397.386033] panel-himax-hx8394 30500000.dsi.0: hx8394_disable: Enter" text in the second output.  I had a bunch of debug lines in the kernel to verify the panel was getting initialized.  I trimmed all but that line out (there is "enable" that happens later on the device open) on the post as the text wasn't needed to convey the issue.

Hi,

Can you please share your dts changes so that we can try replicating the issue on our side.

Hi.  Thanks for taking a look.

Here are the DTS changes (note: we have DSS0 enabled, but nothing connected to it).

&dphy_tx0 {
	bootph-all;
	status = "okay";
};

&dss1 {
	bootph-all;
	status = "okay";
};

&dss1_ports {
	bootph-all;
	#address-cells = <1>;
	#size-cells = <0>;

	/* DSS1-VP1: DSI Output */
	port@1 {
		reg = <1>;

		dss1_dpi1_out: endpoint {
			remote-endpoint = <&dsi0_in>;
		};
	};
};

&dsi0 {
	bootph-all;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			dsi0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};

		port@1 {
			reg = <1>;

			dsi0_in: endpoint {
				remote-endpoint = <&dss1_dpi1_out>;
			};
		};
	};

	dsi_panel0: panel-dsi@0 {
		compatible = "orientdisplay,afy15203b";
		reg = <0>;
		vcc-supply = <&vcc_lcd_5v>;
		iovcc-supply = <&vio_1p8_lcd>;
		reset-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
		backlight = <&backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&dsi0_out>;
			};
		};
	};
};

We have also updated the drivers/gpu/drm/panel/panel-himax-hx8394.c with the following patch to support our specific panel:

diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c
index 631420d28be4..6349fac07799 100644
--- a/drivers/gpu/drm/panel/panel-himax-hx8394.c
+++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c
@@ -52,6 +52,7 @@
 #define HX8394_CMD_SETGIP1	  0xd5
 #define HX8394_CMD_SETGIP2	  0xd6
 #define HX8394_CMD_SETGPO	  0xd6
+#define HX8394_CMD_UNKNOWN4   0xd8
 #define HX8394_CMD_SETSCALING	  0xdd
 #define HX8394_CMD_SETIDLE	  0xdf
 #define HX8394_CMD_SETGAMMA	  0xe0
@@ -86,6 +87,183 @@ static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
 	return container_of(panel, struct hx8394, panel);
 }
 
+static int afy15203b_init_sequence(struct hx8394 *ctx)
+{
+	char buf[4];
+	ssize_t ret;
+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+
+	msleep(50);
+
+	/* fetch ID of Panel.  Try twice in case junk from power on.*/
+	for (int i = 0; i < 2; ++i)
+	{
+
+		msleep(2);
+
+		mipi_dsi_set_maximum_return_packet_size(dsi,4);
+	
+		ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, buf, sizeof(buf));
+		if (ret < 0)
+			dev_err(ctx->dev, "error fetching display panel ID (%ld)\n", ret);
+		else {
+			unsigned int disp_id;
+			disp_id = (buf[0] & 0xFF) << 16;
+			disp_id |= (buf[1] & 0xFF) << 8;
+			disp_id |= (buf[2] & 0xFF);
+			dev_info(ctx->dev, "Display Panel ID len (%ld) was 0x%02X%02X%02X\n", ret, buf[0], buf[1], buf[2]);
+			if (disp_id != 0x0083940F)
+			{
+				dev_err(ctx->dev, "Invalid Panel ID Found (0x%08X)\n", disp_id);
+			}
+		}
+
+		// debug - can remove once we are convinced panel control is OK.
+		ret =  mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_STATUS, buf, sizeof(buf));
+		if (ret < 0)
+			dev_err(ctx->dev, "error fetching display status (%ld)\n", ret);
+		else {
+			dev_info(ctx->dev, "Display status len (%ld) was 0x%02X%02X%02X%02X\n", ret, buf[0], buf[1], buf[2], buf[3]);
+		}
+	}
+
+	/* 5.19.8 SETEXTC: Set extension command (B9h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
+			       0xff, 0x83, 0x94);
+
+	/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
+		0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
+
+		/* 5.19.2 SETPOWER: Set power (B1h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
+			       0x50, 0x12, 0x72, 0x09, 0x33, 0x54, 0xB1, 0x31, 0x6B, 0x2F);
+
+	/* 5.19.3 SETDISP: Set display related register (B2h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
+			       0x00, 0x80, 0x64, 0x0E, 0x0D, 0x2F /* enable these for test pattern, 0x00, 0x00, 0x00, 0x00, 0x48 */);
+
+	/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
+			       0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86, 0x75, 0x00, 0x3F,
+			       0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86);
+
+	/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
+			       0x73,	/* Forward scan VCOM voltage control. (0x77: -1.49V, flk=8%) */
+			       0x73);	/* Backward scan VCOM voltage control. */
+
+	/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
+			       0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x10, 0x00, 0x08, 0x10,
+			       0x08, 0x00, 0x08, 0x54, 0x15, 0x0E, 0x05, 0x0E, 0x02, 0x15,
+			       0x06, 0x05, 0x06, 0x47, 0x44, 0x0A, 0x0A, 0x4B, 0x10, 0x07,
+			       0x07, 0x0E, 0x40);
+
+	/* 5.19.20 Set GIP Option1 (D5h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
+			       0x1A, 0x1A, 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03,
+			       0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
+			       0x24, 0x25, 0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
+			       0x18, 0x18, 0x18, 0x18);
+
+	/* 5.19.21 Set GIP Option2 (D6h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
+			       0x1A, 0x1A, 0x1B, 0x1B, 0x0B, 0x0A, 0x09, 0x08,
+			       0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+			       0x21, 0x20, 0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,
+			       0x18, 0x18, 0x18, 0x18);
+
+
+	/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
+			       0x00, 0x0C, 0x19, 0x20, 0x23, 0x26, 0x29, 0x28,
+			       0x51, 0x61, 0x70, 0x6F, 0x76, 0x86, 0x89, 0x8D,
+			       0x99, 0x9A, 0x95, 0xA1, 0xB0, 0x57, 0x55, 0x58,
+			       0x5C, 0x5E, 0x64, 0x6B, 0x7F, 0x00, 0x0C, 0x18,
+			       0x20, 0x23, 0x26, 0x29, 0x28, 0x51, 0x61, 0x70,
+			       0x6F, 0x76, 0x86, 0x89, 0x8D, 0x99, 0x9A, 0x95,
+			       0xA1, 0xB0, 0x57, 0x55, 0x58, 0x5C, 0x5E, 0x64,
+			       0x6B, 0x7F);
+
+	/* Unknown command (C0h), not listed in the HX8394-F datasheet */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
+			       0x1f, 0x73);
+
+	/* CABC Control1 (C9h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC,
+			       0x76, 0x00, 0x30);
+
+	/* 5.19.17 SETPANEL (CCh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
+			       0x03);
+
+	/* Unknown command (D4h), not listed in the HX8394-F datasheet */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
+			       0x02);
+
+	/* 5.19.11 Set register bank (BDh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
+			       0x02);
+
+	/* Unknown command (D8h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
+			       0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			       0xFF, 0xFF, 0xFF);
+
+	/* 5.19.11 Set register bank (BDh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
+		0x00);
+
+	/* 5.19.11 Set register bank (BDh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
+		0x01);
+
+	/* 5.19.2 SETPOWER: Set power (B1h) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
+			       0x00);
+
+	/* 5.19.11 Set register bank (BDh) */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
+			       0x00);
+
+	/* Unknown command (C6H), not listed in the HX8394-F datasheet */
+	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
+			       0xEF);
+
+    /* Pixel format 24 bit or 16 bit is supported  (3Ah)*/
+	mipi_dsi_dcs_set_pixel_format(dsi, /* MIPI_DCS_PIXEL_FMT_16BIT */ MIPI_DCS_PIXEL_FMT_24BIT );
+
+	return 0;
+}
+
+static const struct drm_display_mode afy15203b_mode = {
+	.hdisplay    = 720,
+	.hsync_start = 720 + 18,
+	.hsync_end   = 720 + 18 + 36,
+	.htotal	     = 720 + 18 + 36 + 18,
+	.vdisplay    = 1280,
+	.vsync_start = 1280 + 12,
+	.vsync_end   = 1280 + 12 + 4,
+	.vtotal	     = 1280 + 12 + 4 + 15,
+	.clock	     = ( 720 + 18 + 36 + 18) * (1280 + 12 + 4 + 15) * 60 / 1000, // total / frame pixel clock in KHZ?
+	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+	.width_mm    = 62,
+	.height_mm   = 110,
+};
+
+static const struct hx8394_panel_desc afy15203b_desc = {
+	.mode = &afy15203b_mode,
+	.lanes = 4,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_HSE/* | MIPI_DSI_MODE_VIDEO_BURST -- not supported by TI's DSI driver*/, 
+	.format = MIPI_DSI_FMT_RGB888, /* MIPI_DSI_FMT_RGB565, */
+	.init_sequence = afy15203b_init_sequence,
+};
+
 static int hsd060bhw4_init_sequence(struct hx8394 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
@@ -208,6 +386,7 @@ static int hx8394_enable(struct drm_panel *panel)
 	struct hx8394 *ctx = panel_to_hx8394(panel);
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 	int ret;
+	char buf[4];
 
 	ret = ctx->desc->init_sequence(ctx);
 	if (ret) {
@@ -230,6 +409,15 @@ static int hx8394_enable(struct drm_panel *panel)
 		goto sleep_in;
 	}
 
+	msleep(10);
+
+	ret =  mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_STATUS, buf, sizeof(buf));
+	if (ret < 0)
+		dev_err(ctx->dev, "error fetching display status (%ld)\n", ret);
+	else {
+		dev_info(ctx->dev, "Display status len (%ld) was 0x%02X%02X%02X%02X\n", ret, buf[0], buf[1], buf[2], buf[3]);
+	}
+
 	return 0;
 
 sleep_in:
@@ -430,6 +618,7 @@ static void hx8394_remove(struct mipi_dsi_device *dsi)
 
 static const struct of_device_id hx8394_of_match[] = {
 	{ .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
+	{ .compatible = "orientdisplay,afy15203b", .data = &afy15203b_desc },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, hx8394_of_match);

Please le me know if you need more information.

I am working through the driver code to understand how all the clock / tree works and is setup.  I am hoping it is a simple fix / user error.

With regards,

Mike

BTW we tried to follow the "microtips,mf-070zimacaa0" panel example in k3-am62p5-sk-microtips-mf070zima-lcd3.dtso

Thanks, 

Let me take a look into it. Will get back to you by mid-next week.

Hi,

I am still trying to replicate your issue. Meanwhile, can you share any quick way to replicate this. Please also mention the panel that you are using.

We are using afy15203b from Orient Display, which is being driven by a Himax HX8394-F 720x1280 DSI to TFT Mobile Chip driver.  The customer has a high volume of these in stock from a lifecycle order.  For the AM335x, they were using an external DPI to MIPI DSI bridge chip.  They would like to eliminate the bridge chip.

We have a small adapter card to connect the display to MitySOM-AM62P developers kit (a custom board from TI's perspective) to the DSI lanes.

I don't know if the AM62P EVM from TI has access to the DSI lanes, I could look into adapting a board for that and get a panel to you if it comes to that.

I think uou should be able to configure the EVM with this panel an enable the display with nothing connected and check for activity on the Data Lanes?  Though without termination and proper ack packets perhaps that will not work.  I am wondering if we don't have some of the clock or data paths configured correctly. 

Hi,

I am assuming that the timing parameter that you are using are from the panel vendor's datasheet. Just as an experiment to confirm the issue, can you please try tuning and playing around with these timing numbers and then check if you are able to get to the originally desired frequency in k3conf?

Yes, the timing parameters are from an existing design based on the datasheet.

The number I am loading into the drm_display_mode structure in the panel driver is 62298720 Hz but K3CONF is reporting 62254901 Hz.  This is consistent with the 59.9 Hz reported in the kmstest run.  Are you asking me to tweak the panel parameters so that I get the same 62254901 rate?  I will try and see if anything changes and report back.

There doesn't appear to be a clock tree tool available yet for the AM62P, so it's not entirely clear how the clocking works between the DPI1 and the DSI PHY clock rates.  I would assume they would be based on the DPI1 clock rate, the number of lanes, and the bpp. I added a print out in the cdns_dsi_check_conf() routine that suggests it is computing a HS_CLK_RATE of 373,788,000 Hz, which seems consistent with DPI1 clock * 24 bpp / 4 DSI lanes (373,529,406).  But I don't see that clock anywhere in the K3CONF dump clocks command when the system is running.  I would expect that to be on DEV_DSS_DSI0_DPI_0_CLK or DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK, right?  Both of those clocks are reporting 0 on k3conf dump.  Perhaps k3conf doesn't decode those properly, or the clocks aren't out of reset?

Michael Williamson said:

But I don't see that clock anywhere in the K3CONF dump clocks command when the system is running.  I would expect that to be on DEV_DSS_DSI0_DPI_0_CLK or DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK, right?

Thanks for the detailed explanation, I had slightly misunderstood your question. I have been able to validate your observations on my end and will share with the respective team.
But since you are able to see the clocks through cdns_dsi_check_conf, I expect your DSI to be functional, but only the k3conf not getting populated. Is this assumption correct?

So I did a fair amount of experimenting yesterday.  No amount of adjusting the clocking (porch widths, etc., even dropping frame rate down to 30 Hz) seemed to change the situation.

I went and got a high speed scope.  I am now able to see a continuous ~186 MHz clock on the clock lane, which seems correct if it is a DDR interface.  But all of the data lanes appear to be in the Low Power state (there is no activity I can see with the scope) at about 1.8V, almost like they are powered down or stuck in reset.

When I look at the MCTL_DPHY_CFG0 register:

root@mitysom-am62px:~# k3conf read 0x30500010 32
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62Px SR1.0                                                        |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

Value at addr 0x30500010 = 0x1f03f1

It looks like all of the lanes are powered down?  Though the TRM is unclear about the use of these bits:

The value of 0x1F03F1:

DPHY_CMN_PSO is enabled

DPHY_PLL_PSO is disable

DPHY_D_PDN, DPHY_C_PDN, DPHY_CMN_PDC are all set high.  Is this Powered Down, or Powered on?

DPHY_PLL_PDN is set low.  Is this powered down, or powered on?

It looks like all of the clock and data pins are out of reset (assuming RSTB means active low, but it's not well documented).

Any suggestions to try to get the DPHY data lanes to start pumping data is welcome.

Thanks!

Mike

Michael Williamson said:

The value of 0x1F03F1

I'll share my register dump with you by tomorrow for comparison.
But I am confused a little bit with your question. You mentioned you are not seeing data on DPHY data line, meaning you are not seeing anything on the DSI display?
Since earlier you showed kmstest console logs working correctly, I assume you are able to see something on display.

Using the kmstest or manipulating the framebuffer (or running weston) results in a blank screen when the system should be transmitting DSI HS video data, even though kmstest shows a running framerate.  Scoping the lines seems to show no data from the DSI data TX pairs from the processor.  However, the LP commands work as I can command the display to enter test pattern mode, but that is running data from the local MIPI DSI->controller bridge on the display, not from the AM62P.

I have not seen a valid kmstest pattern on the display (or anything else from the AM62P).

I am assuming you are using a custom board with AM62P SoC. 
Have you yet validated the Raspberri Pi 7inch touch DSI display panel with your board? Asking this because we have tested drivers for that and it can help us isolate the issue.

We have not.  The flex interface cables are not compatible, and there is not I2C command bus (it must be commanded / setup via the DSI LP interface).

We would have to make a custom board to support the Raspberri Pi 7 Inch display.

We might be able to "fake" it and see if we can get the DSI lanes to drive using a Raspberry pi configuration, but I suspect the probe will fail looking for I2C command interface the Pi Display uses.

Sorry:

...  there is no I2C command bus on the target display we are using (it must be commanded / setup via the DSI LP interface). 

It's close to the microtips display that appears to have a overlay DTB setup for: k3-am62p5-sk-microtips-mf070zima-lcd3.dtso. 

Has that been validated?

Michael Williamson said:

When I look at the MCTL_DPHY_CFG0 register:

This is what I see:

root@am62pxx-evm:~# k3conf read 0x30500010 32
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62Px SR1.0                                                        |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.8--v10.01.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

Value at addr 0x30500010 = 0x1103f1

Michael Williamson said:

Has that been validated?

Yes, that dtso has been validated as well.

Is this with the Raspberry Pi display running kmsprint or other active output?

Yes, kmstest is running in background.

Hello,

Is there anyway to validate that the DPI->DSI gearbox thinks it is working OK?

I have dumped out the value of the  DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS (0x305000F0) when the kmstest is running and I am getting a value of 0x4 which says there is an "ERR_MISSING_HSYNC" status.  However, it looks like the  DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS_CTL (0x30500140) is set to all zeros, so I am not sure the status register is valid.

This is behaving like the gearbox is not happy or is not receiving data properly from the DPI interface and just not generating any data.

In my example, the clock rate for the DPI is being set at 62254901 (24 bits per pixel)

The clock rate generated by the PLL DSI data bit rate is 375000000 (4 lanes, 3 bytes per pixel).

The data ratio (bits/sec) between the DSI : DPI is 1.003937023 (the DSI clocking is slightly faster than the DPI clocking).

I am looking at the vertical parameters between what is sent to the DPI (via the panel parameters) and what is programmed into the DSI VACT (height), VFP, VBP, and VSA (VSYNC) and I am noting that the number of VFP lines programmed in the DSI is the same as the DPI.

Reading the TRM, section 12.9.2.7.9, the last paragraph suggests that the DSI VFP should be 1 less than that of the DPI:

" The controller works by transitioning to LP during the last programmed line of VFP. It will then remain in LP until the start of the next frame. So programming the controller to match the DPI, but with at least one fewer line of VFP should result in a reliable configuration."

I think something may not be correct in the driver here.

Hi,

There are a few patches for the cdns driver available at: https://lore.kernel.org/all/20250320-cdns-dsi-impro-v1-18-725277c5f43b@ideasonboard.com/#r. These haven't been upstreamed yet, and hence not included in current SDK.
We are yet to test these out on our setups, but you may try testing them on your end parallely.

I pulled in that patch set. It wasn't clean, the pending patches are on top of drm-misc-next which is well ahead of the TI 6.6 or 6.12 branches.

I am still not seeing any output on the DSI data lanes when running kmstest, just a clock.

I have tried a couple of different boards here to make sure that I somehow didn't damage the DSI output lanes.  I just don't see any data coming out of the part.

Hi,

DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS (0x305000F0) value is 0x1 for me, while DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS_CTL (0x30500140) is 0x0.
I may need to start a ticket with the DSI DPHY IP provider, but before we do that, have you verified your display working with any other board?

It works with the original AM335x design using an external MIPI bridge chip to convert DPI output from AM225x to DSI input on panel.

Can you run your test using the Microtips example?  The Rasp. PI display is running 1 lane at a much higher clock rate vs. the 4 lanes at a lower clock rate.  So it's fairly different from the DSI gearbox perspective. The Microtips more closely matches what we are trying to do.  I actually tried using the timing from the Microtips panel to see if I could see anything but I had the same behavior.

Hi,

Michael Williamson said:

Can you run your test using the Microtips example?

Sure, please find the below results with Microtips LCD3 DSI panel.

root@am62pxx-evm:~# kmsprint --device=/dev/dri/card2
Connector 0 (40) DSI-1 (connected)
  Encoder 0 (39) NONE
    Crtc 0 (38) 800x1280@60.01 82.550 800/100/32/100/? 1280/20/3/30/? 60 (60.01) 0x0 0x48
      Plane 0 (31) fb-id: 50 (crtcs: 0) 0,0 800x1280 -> 0,0 800x1280 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
        FB 50 800x1280
root@am62pxx-evm:~# kmstest --device=/dev/dri/card2 &
[1] 1257
root@am62pxx-evm:~# Connector 0/@40: DSI-1
  Crtc 0/@38: 800x1280@60.01 82.550 800/100/32/100/? 1280/20/3/30/? 60 (60.01) 0x0 0x48
  Plane 0/@31: 0,0-800x1280
    Fb 50 800x1280-XR24
press enter to exit
root@am62pxx-evm:~# k3conf read 0x30500010 32
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62Px SR1.0                                                        |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.8--v10.01.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

Value at addr 0x30500010 = 0x1f03f1

root@am62pxx-evm:~# k3conf read 0x305000F0
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62Px SR1.0                                                        |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.8--v10.01.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

Value at addr 0x305000f0 = 0x1

root@am62pxx-evm:~# k3conf read 0x30500140
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62Px SR1.0                                                        |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.1.8--v10.01.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

Value at addr 0x30500140 = 0x0

MCTL_DPHY_CFG0 value is correct since bits [19:16]=0xf implies all 4 lanes are asserted to work.
DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS (0x305000F0) value is still 0x1 for me.
DSI_VBUSP_CFG_DSI_0_DSI_VID_MODE_STS_CTL (0x30500140) is 0x0 same as yours.

Thanks for running this.

I am noting that you are seeing the drm device should on on /dev/dri/card2.

My device is showing up on /dev/dri/card0.

Is it possible that my device is running on the wrong DPI port (and thus not connected to the DSI input)?  This would suggest a device tree problem?

No, this mostly depends on which drm device gets probed first in kernel boot. Whichever is done first gets allotted the lowest number in /dev/dri/cardX.
Since your kmsprint/kmstest shows DSI connected with card0, this should not be an issue.
I will create a ticket with Cadence on how to debug this issue. Can you please summarize here once again with the dts and/or driver changes (including any modifications you did from last time), your panel vendor datasheet for timing parameters, what all you have in the display pipeline outside of AM62P SoC and any dss related logs in the dmesg.

We are using TI's 6.6.y kernel corresponding to SDK 10.0.0.7 (I believe, that latest one for the AM62P support).

This our device tree, the relevant panel enablement is at the end.  I get the same behavior if I enable the microtips panel instead of the orientdisplay panel (but in the case of the microtips panel, I have to unplug the orientdisplay panel because it has to be programmed soon after power on correclty or you can damage the display).

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for the MitySom-AM62Px Devkit
 */

/dts-v1/;

#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include "k3-am62px-mitysom-som.dtsi"

/ {
	vcc_12v: vcc_12v {
		compatible = "regulator-fixed";
		regulator-name = "vcc_12v";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0: vcc_5v0 {
		/* MIC24052 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc_12v>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_3v3: vcc_3v3 {
		/* MIC24052 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_12v>;
		regulator-always-on;
		regulator-boot-on;
	};

	vin_3v3_som: vin_3v3_som {
		/* 3.3V SOM VIN */
		compatible = "regulator-fixed";
		regulator-name = "vin_3v3_som";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_3v3_vio: vcc_3v3_vio {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_vio";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&som_vdd_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0_can0: vcc_5v0_can0 {
		/* VIBLSD1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0_can0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc_12v>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_5v0_can1: vcc_5v0_can1 {
		/* VIBLSD1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_5v0_can1";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc_12v>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_1v1_usbhub: vcc_1v1_usbhub {
		/* RT5796 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v1_usbhub";
		regulator-min-microvolt = <1100000>;
		regulator-max-microvolt = <1100000>;
		vin-supply = <&vcc_5v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_1v2_eth: vcc_1v2_eth {
		/* RT5796 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v2_eth";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		vin-supply = <&vcc_5v0>;
		regulator-always-on;
		regulator-boot-on;
	};


	vdd_mmc1: vdd_mmc1 {
		/* TPS2051 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vcc_3v3_vio>;
	};

	som_vdd_sd_dv: som_vdd_sd_dv {
		/* Output of TPS65219. Switches voltage for SD card */
		bootph-all;
		compatible = "regulator-gpio";
		regulator-name = "vsel_sd";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_pins_default>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		// vin-supply = <&ldo1>;
		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	vcc_lcd_5v: vcc_lcd_5v {
		compatible = "regulator-fixed";
		regulator-name = "lcd_5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&exp2 1 GPIO_ACTIVE_LOW>;
		startup-delay-us = <10000>;
		// enable-active-high;
		vin-supply = <&vcc_12v>;
	};

	vio_1p8_lcd: vio_1p8_lcd {
		compatible = "regulator-fixed";
		regulator-name = "vio_1p8_lcd";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc_3v3_vio>;
		regulator-always-on;
		regulator-boot-on;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&epwm0 0 50000 0>;
		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
		default-brightness-level = <8>;
		power-supply = <&vcc_12v>;
	};

	tlv320_mclk: clk-0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24576000>;
	};

	codec_audio: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "AM62x";
		simple-audio-card,widgets =
			"Headphone",	"Headphone Jack",
			"Microphone",	"Microphone Jack";
		simple-audio-card,routing =
			"Headphone Jack",	"HPL",
			"Headphone Jack",	"HPR",
			"MICIN",		"Microphone Jack";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;
		/* simple-audio-card,bitclock-inversion; */

		simple-audio-card,cpu {
			sound-dai = <&mcasp0>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic26>;
			clocks = <&tlv320_mclk>;
		};
	};

	/* D1 DBG_LED on devkit located above the USB hub ports */
	leds {
		compatible = "pwm-leds";

		led-0 {
			label = "devkit-d1";
			pwms = <&main_pwm7 0 7812500 0>;
			max-brightness = <255>;
			color = <LED_COLOR_ID_GREEN>;
			linux,default-trigger = "heartbeat";
			function = LED_FUNCTION_HEARTBEAT;
			default-state = "off";
			active-low;
		};
	};

	main_pwm7: dmtimer-main-pwm-7 {
		pinctrl-0 = <&usr_led_pins_default>;
		pinctrl-names = "default";
		compatible = "ti,omap-dmtimer-pwm";
		#pwm-cells = <3>;
		ti,timers = <&main_timer7>;
	};

	hdmi0: connector-hdmi  {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";
		ddc-i2c-bus = <&main_i2c1>;
		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tfp410_out>;
			};
		};
	};

	usb_micro_con: usb_microb_connector {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		type = "micro";
		label = "USB Micro Connector";

		id-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
		port@0 {
			reg = <0>;
			usb_micro_con_in: endpoint {
				remote-endpoint = <&microb>;
			};
		};
	};
};

&main_pmx0 {
	bootph-all;

	pinctrl-names = "default";
	pinctrl-0 = <&main_system_pins_default &main_gpio_p3_pins_default>;

	baseboard_ioexp_intr_pins_default: baseboard-ioexp-intr-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 PCA_INT_N */
		>;
	};

	main_i2c1_pins_default: main-i2c1-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
			AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */
		>;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */
			AM62PX_IOPAD(0x0234, PIN_INPUT, 0) /* (J24) MMC1_CLK */
			AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */
			AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */
			AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */
			AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */
			AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */
		>;
	};

	main_mmc2_pins_default: main-mmc2-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */
			AM62PX_IOPAD(0x0118, PIN_INPUT, 0) /* (K21) MMC2_CLK */
			AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */
			AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */
			AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */
			AM62PX_IOPAD(0x0108, PIN_INPUT, 0) /* (L21) MMC2_DAT3 */
			AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */
		>;
	};

	main_mdio1_pins_default: main-mdio1-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
			AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
		>;
	};

	main_rgmii1_pins_default: main-rgmii1-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
			AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
			AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
			AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
			AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
			AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
			AM62PX_IOPAD(0x0134, PIN_OUTPUT, 0) /* (A18) RGMII1_TD0 */
			AM62PX_IOPAD(0x0138, PIN_OUTPUT, 0) /* (C17) RGMII1_TD1 */
			AM62PX_IOPAD(0x013c, PIN_OUTPUT, 0) /* (A17) RGMII1_TD2 */
			AM62PX_IOPAD(0x0140, PIN_OUTPUT, 0) /* (C16) RGMII1_TD3 */
			AM62PX_IOPAD(0x0130, PIN_OUTPUT, 0) /* (B17) RGMII1_TXC */
			AM62PX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (B18) RGMII1_TX_CTL */
		>;
	};

	main_rgmii2_pins_default: main-rgmii2-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */
			AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */
			AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */
			AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */
			AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */
			AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */
			AM62PX_IOPAD(0x016c, PIN_OUTPUT, 0) /* (B19) RGMII2_TD0 */
			AM62PX_IOPAD(0x0170, PIN_OUTPUT, 0) /* (A21) RGMII2_TD1 */
			AM62PX_IOPAD(0x0174, PIN_OUTPUT, 0) /* (D17) RGMII2_TD2 */
			AM62PX_IOPAD(0x0178, PIN_OUTPUT, 0) /* (A19) RGMII2_TD3 */
			AM62PX_IOPAD(0x0168, PIN_OUTPUT, 0) /* (D16) RGMII2_TXC */
			AM62PX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (A20) RGMII2_TX_CTL */
		>;
	};

	main_dss0_pins_default: main-dss0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0100, PIN_OUTPUT, 0) /* (W20) VOUT0_VSYNC */
			AM62PX_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AC20) VOUT0_HSYNC */
			AM62PX_IOPAD(0x0104, PIN_OUTPUT, 0) /* (Y21) VOUT0_PCLK */
			AM62PX_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (W21) VOUT0_DE */
			AM62PX_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (AE24) VOUT0_DATA0 */
			AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (W23) VOUT0_DATA1 */
			AM62PX_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA2 */
			AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA3 */
			AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (AB23) VOUT0_DATA4 */
			AM62PX_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (AD23) VOUT0_DATA5 */
			AM62PX_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (AC23) VOUT0_DATA6 */
			AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AE23) VOUT0_DATA7 */
			AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (AE22) VOUT0_DATA8 */
			AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (AC22) VOUT0_DATA9 */
			AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (W22) VOUT0_DATA10 */
			AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AE21) VOUT0_DATA11 */
			AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AD21) VOUT0_DATA12 */
			AM62PX_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AC21) VOUT0_DATA13 */
			AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (AA20) VOUT0_DATA14 */
			AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (Y20) VOUT0_DATA15 */
			AM62PX_IOPAD(0x005c, PIN_OUTPUT, 1) /* (AC25) GPMC0_AD8.VOUT0_DATA16 */
			AM62PX_IOPAD(0x0060, PIN_OUTPUT, 1) /* (AB25) GPMC0_AD9.VOUT0_DATA17 */
			AM62PX_IOPAD(0x0064, PIN_OUTPUT, 1) /* (AA25) GPMC0_AD10.VOUT0_DATA18 */
			AM62PX_IOPAD(0x0068, PIN_OUTPUT, 1) /* (W24) GPMC0_AD11.VOUT0_DATA19 */
			AM62PX_IOPAD(0x006c, PIN_OUTPUT, 1) /* (Y24) GPMC0_AD12.VOUT0_DATA20 */
			AM62PX_IOPAD(0x0070, PIN_OUTPUT, 1) /* (AD25) GPMC0_AD13.VOUT0_DATA21 */
			AM62PX_IOPAD(0x0074, PIN_OUTPUT, 1) /* (AB24) GPMC0_AD14.VOUT0_DATA22 */
			AM62PX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (AC24) GPMC0_AD15.VOUT0_DATA23 */
		>;
	};

	main_spi0_pins_default: spi0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01bc, PIN_INPUT, 0) /* (B21) SPI0_CLK */
			AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
			AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
			AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (E20) SPI0_CS1 */
		>;
	};

	mcasp0_pins_default: mcasp0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) AUDIO_EXT_REFCLK1  */
			AM62PX_IOPAD(0x01a4, PIN_INPUT, 0) /* (F24) MCASP0_ACLKX */
			AM62PX_IOPAD(0x01a8, PIN_INPUT, 0) /* (F25) MCASP0_AFSX */
			AM62PX_IOPAD(0x01a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */
			AM62PX_IOPAD(0x019c, PIN_INPUT, 0) /* (E24) MCASP0_AXR1 */
		>;
	};

	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 VSEL_SD */
		>;
	};

	usb0_pins_default: usb0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 USB0_ID external pullup */
			AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 USB0_OC external pullup */
		>;
	};

	usr_led_pins_default: usr-led-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0244, PIN_OUTPUT, 2) /* (D24) MMC1_SDWP.TIMER_IO7 DBG_LED D1 */
		>;
	};

	oldi_backlight_pins_default: epwm0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			/* J5 Connector */
			AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 6) /* (G23) MCASP0_AFSR.EHRPWM0_A OLDI_PWM */
		>;
	};

	main_system_pins_default: main-system-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0250, PIN_OUTPUT, 0) /* (H24) PORz_OUT */
			AM62PX_IOPAD(0x024c, PIN_OUTPUT, 0) /* (G25) RESETSTATz */
			AM62PX_IOPAD(0x0248, PIN_INPUT, 0) /* (G24) RESET_REQz */
		>;
	};

	main_gpio_p3_pins_default: gpio-p3-default-pins {
		pinctrl-single,pins = <
			/* P3 Connector */
			AM62PX_IOPAD(0x003c, PIN_INPUT_PULLDOWN, 7) /* (U22) GPMC0_AD0.GPIO0_15 */
			AM62PX_IOPAD(0x0040, PIN_INPUT_PULLDOWN, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
			AM62PX_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) /* (U20) GPMC0_AD2.GPIO0_17 */
			AM62PX_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) /* (V25) GPMC0_AD3.GPIO0_18 */
			AM62PX_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7) /* (T20) GPMC0_AD4.GPIO0_19 */
			AM62PX_IOPAD(0x0050, PIN_INPUT_PULLDOWN, 7) /* (T21) GPMC0_AD5.GPIO0_20 */
			AM62PX_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) /* (V24) GPMC0_AD6.GPIO0_21 */
			AM62PX_IOPAD(0x0058, PIN_INPUT_PULLDOWN, 7) /* (W25) GPMC0_AD7.GPIO0_22 */
			AM62PX_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) /* (R25) GPMC0_ADVn_ALE.GPIO0_32 */
			AM62PX_IOPAD(0x0088, PIN_INPUT_PULLDOWN, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */
			AM62PX_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7) /* (T25) GPMC0_WEn.GPIO0_34 */
			AM62PX_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) /* (U24) GPMC0_BE0n_CLE.GPIO0_35 */
			AM62PX_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */
			AM62PX_IOPAD(0x00a4, PIN_INPUT_PULLDOWN, 7) /* (P25) GPMC0_DIR.GPIO0_40 */
			AM62PX_IOPAD(0x00a8, PIN_INPUT_PULLDOWN, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */
			AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLDOWN, 7) /* (T22) GPMC0_CSn2.GPIO0_43 */
			AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLDOWN, 7) /* (U25) GPMC0_CSn3.GPIO0_44 */
			AM62PX_IOPAD(0x0194, PIN_INPUT_PULLDOWN, 7) /* (D25) MCASP0_AXR3.GPIO1_7 */
			AM62PX_IOPAD(0x0198, PIN_INPUT_PULLDOWN, 7) /* (E25) MCASP0_AXR2.GPIO1_8 */
			AM62PX_IOPAD(0x01b4, PIN_INPUT_PULLDOWN, 7) /* (D20) SPI0_CS0.GPIO1_15 */
			AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLDOWN, 7) /* (A23) UART0_CTSn.GPIO1_22 */
			AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLDOWN, 7) /* (C22) UART0_RTSn.GPIO1_23 */
			AM62PX_IOPAD(0x01d8, PIN_INPUT_PULLDOWN, 7) /* (B23) MCAN0_TX.GPIO1_24 */
			AM62PX_IOPAD(0x01dc, PIN_INPUT_PULLDOWN, 7) /* (F20) MCAN0_RX.GPIO1_25 */
			AM62PX_IOPAD(0x01f0, PIN_INPUT_PULLDOWN, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */
		>;
	};
};

&mcu_pmx0 {
	pinctrl-names = "default";
	pinctrl-0 = <&som_mcu_system_pins_default &mcu_jtag_pins_default &mcu_uart1_pins_default &mcu_system_pins_default &mcu_gpio_p3_pins_default>;

	mcu_jtag_pins_default: jtag-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0078, PIN_INPUT_PULLUP, 0) /* (B12) EMU0 */
			AM62PX_MCU_IOPAD(0x007c, PIN_INPUT_PULLUP, 0) /* (D13) EMU1 */
			AM62PX_MCU_IOPAD(0x0064, PIN_INPUT_PULLUP, 0) /* (C13) TCK */
			AM62PX_MCU_IOPAD(0x006c, PIN_INPUT_PULLUP, 0) /* (E13) TDI */
			AM62PX_MCU_IOPAD(0x0070, PIN_OUTPUT_PULLUP, 0) /* (C14) TDO */
			AM62PX_MCU_IOPAD(0x0074, PIN_INPUT_PULLUP, 0) /* (E14) TMS */
			AM62PX_MCU_IOPAD(0x0068, PIN_INPUT_PULLDOWN, 0) /* (B13) TRSTn */
		>;
	};

	mcu_oldi_touch_pins_default: oldi-touch-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (B8) MCU_UART0_CTSn.MCU_GPIO0_7 OLDI_IRQ_N external pullup */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */
			AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */
			AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (E8) MCU_MCAN1_TX */
		>;
	};

	bt_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD BT_UART_RX */
			AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD BT_UART_TX */
			AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn BT_UART_CTS */
			AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn BT_UART_RTS */
		>;
	};

	mcu_uart1_pins_default: mcu-uart1-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* (B6) MCU_UART0_RXD */
			AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (C8) MCU_UART0_TXD */
		>;
	};

	mcu_system_pins_default: mcu-system-default-pins {
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0054, PIN_INPUT_PULLUP, 0) /* (F11) MCU_RESETz external pullup */
			AM62PX_MCU_IOPAD(0x005c, PIN_OUTPUT, 0) /* (F14) MCU_RESETSTATz */
		>;
	};

	mcu_gpio_p3_pins_default: mcu-p3-default-pins {
		pinctrl-single,pins = <
			/* P3 Connector */
			AM62PX_MCU_IOPAD(0x0000, PIN_INPUT_PULLDOWN, 7) /* (B10) MCU_SPI0_CS0.MCU_GPIO0_0 */
			AM62PX_MCU_IOPAD(0x0004, PIN_INPUT_PULLDOWN, 7) /* (E10) MCU_SPI0_CS1.MCU_GPIO0_1 */
			AM62PX_MCU_IOPAD(0x0008, PIN_INPUT_PULLDOWN, 7) /* (C10) MCU_SPI0_CLK.MCU_GPIO0_2 */
			AM62PX_MCU_IOPAD(0x000c, PIN_INPUT_PULLDOWN, 7) /* (B11) MCU_SPI0_D0.MCU_GPIO0_3 */
			AM62PX_MCU_IOPAD(0x0010, PIN_INPUT_PULLDOWN, 7) /* (D10) MCU_SPI0_D1.MCU_GPIO0_4 */
			AM62PX_MCU_IOPAD(0x0044, PIN_INPUT, 7) /* (E11) MCU_I2C0_SCL.MCU_GPIO0_17 */
			AM62PX_MCU_IOPAD(0x0048, PIN_INPUT, 7) /* (D11) MCU_I2C0_SDA.MCU_GPIO0_18 */
			AM62PX_MCU_IOPAD(0x004c, PIN_INPUT, 7) /* (A13) WKUP_I2C0_SCL.MCU_GPIO0_19 */
			AM62PX_MCU_IOPAD(0x0050, PIN_INPUT, 7) /* (C11) WKUP_I2C0_SDA.MCU_GPIO0_20 */
		>;
	};
};

&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <100000>;
	bootph-all;

	/* MIPI Raspberry Pi Camera V2 0x10 */

	/* GPIO expander 0x20 */
	exp1: gpio@20 {
		bootph-all;
		compatible = "nxp,pcal6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names =
					"ETH1_INT_N", "ETH2_INT_N",
					"TFP410_RESET_N", "OLDI_RESETN",
					"ETH2_RESETN", "ETH1_RESETN",
					"WLAN_BT_EN", "AUDIO_RESET_N";

		interrupt-parent = <&main_gpio0>;
		interrupts = <42 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&baseboard_ioexp_intr_pins_default>;
	};

	/* TFP410 HDMI transmitter 0x38 */
	hdmi_encoder: tfp410@38 {
		status = "disabled";
		compatible = "ti,tfp410";
		reg = <0x38>;
		/* u-boot handles the reset */
		/* reset-gpios = <&exp1 2 GPIO_ACTIVE_LOW>; */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tfp410_in: endpoint {
					remote-endpoint = <&dpi1_out>;
				};
			};

			port@1 {
				reg = <1>;

				tfp410_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	/* HDMI EDID 0x50 */

	/* Power Monitor 0x6F */
	ltc2945@6f {
		status = "okay";
		compatible =  "adi,ltc2945";
		reg = <0x6f>;
		// 1000 microOhms is the default
		shunt-resistor-micro-ohms = <20000>;
	};

	/* P3 Expansion Header */

	/* MAX7325 with interrupt support disabled 0x26 */
	exp2: gpio@26 {
		status = "okay";
		compatible = "maxim,max7315";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "LCD_RESET_N", "LCD_PWR_ENABLE";
	};

	/* touchscreen - TODO same address as TFP410!!! */

};

&main_i2c2 {
	status = "disabled";
};

&main_i2c3 {
	status = "disabled";
};

&main_spi0 {
	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_spi0_pins_default>;
 	ti,spi-num-cs = <2>;
 	ti,pindir-d0-out-d1-in;
 	tlv320aic26: audio-codec@1 {
 		status = "okay";
 		#sound-dai-cells = <0>;
 		compatible = "ti,tlv320aic26";
 		reg = <0x1>;
 		/* Regulators */
 		AVDD-supply = <&vcc_3v3_vio>;
 		IOVDD-supply = <&vcc_3v3_vio>;
 		DRVDD-supply = <&vcc_3v3_vio>;
 		DVDD-supply = <&som_vdd_1v8>;
 		reset-gpios = <&exp1 7 GPIO_ACTIVE_LOW>;
 		spi-max-frequency = <1000000>;
 		spi-cpha;
 	};
 };

&sdhci1 {
	/* SD/MMC */
	bootph-all;
	status = "okay";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&som_vdd_sd_dv>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	disable-wp;
	/* Disable 1.8V mode when VSEL_SD is not controllable */
	/* no-1-8-v; */
};

&usbss0 {
	bootph-all;
	status = "okay";
	ti,vbus-divider;
};

&usbss1 {
	status = "okay";
	ti,vbus-divider;
};

&usb0 {
	bootph-all;
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&som_usb0_pins_default
				&usb0_pins_default>;
	dr_mode = "otg";
	usb-role-switch;

	port@0 {
		reg = <0>;

		microb: endpoint {
			remote-endpoint = <&usb_micro_con_in>;
		};
	};
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&som_usb1_pins_default>;
	dr_mode = "host";

	usb_hub: connector {
		compatible = "usb-a-connector";
	};
};

&cpsw3g {
	bootph-all;
	pinctrl-names = "default";
	pinctrl-0 = <&main_rgmii1_pins_default
		     &main_rgmii2_pins_default>;
};

&cpsw_port1 {
	bootph-all;
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw_port2 {
	bootph-all;
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};

&cpsw3g_mdio {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mdio1_pins_default>;

	cpsw3g_phy0: ethernet-phy@3 {
		bootph-all;
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};

	cpsw3g_phy1: ethernet-phy@4 {
		bootph-all;
		reg = <4>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&dss_oldi_io_ctrl {
	bootph-all;
};

&dss0 {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_dss0_pins_default>;
};

&dss0_ports {
	/* see Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml */
	/* VP0: LVDS Output (OLDI TX 0) */
	/* VP1: DPI Output */
	hdmi0_dss: port@1 {
		reg = <1>;
		dpi1_out: endpoint {
			remote-endpoint = <&tfp410_in>;
		};
	};
};

&mcasp0 {
	status = "okay";
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins_default>;
	op-mode = <0>; /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
	       1 2 0 0
	       0 0 0 0
	       0 0 0 0
	       0 0 0 0
	>;
	tx-num-evt = <0>;
	rx-num-evt = <0>;
	/* auxclk-fs-ratio = <2>; */
};

&epwm0 {
	bootph-all;
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&oldi_backlight_pins_default>;
};

/* mcu_gpio0 and mcu_gpio_intr are shared by P3 expansion and Wifi */
&mcu_gpio0 {
	status = "okay";
};

&mcu_gpio_intr {
	status = "okay";
};

&dphy_tx0 {
	bootph-all;
	status = "okay";
};

&dss1 {
	bootph-all;
	status = "okay";
};

&dss1_ports {
	bootph-all;
	#address-cells = <1>;
	#size-cells = <0>;

	/* DSS1-VP1: DSI Output */
	port@1 {
		reg = <1>;

		dss1_dpi1_out: endpoint {
			remote-endpoint = <&dsi0_in>;
		};
	};
};

&dsi0 {
	bootph-all;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			dsi0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};

		port@1 {
			reg = <1>;

			dsi0_in: endpoint {
				remote-endpoint = <&dss1_dpi1_out>;
			};
		};
	};

/*
	dsi_panel0: panel-dsi@0 {
		compatible = "microtips,mf-070zimacaa0", "ilitek,ili9881c";
		reg = <0>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&dsi0_out>;
			};
		};
	};
*/
	dsi_panel0: panel-dsi@0 {
		compatible = "orientdisplay,afy15203b";
		reg = <0>;
		vcc-supply = <&vcc_lcd_5v>;
		iovcc-supply = <&vio_1p8_lcd>;
		reset-gpios = <&exp2 0 GPIO_ACTIVE_LOW>;
		backlight = <&backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&dsi0_out>;
			};
		};
	};
};

This device tree loads a second dtsi for our SOM (nothing interesting here, but for completeness)

// SPDX-License-Identifier: GPL-2.0
/*
 * Common dtsi for MitySOM-AM62Px
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "k3-am62p5.dtsi"

/ {
	compatible =  "criticallink,mitysom-am62px", "ti,am62p5";
	model = "Critical Link MitySOM-AM62Px";

	aliases {
		serial0 = &wkup_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
		mmc2 = &sdhci2;
		spi0 = &ospi0;
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		usb0 = &usb0;
		usb1 = &usb1;
	};

	chosen {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		stdout-path = &main_uart0;

		framebuffer0: framebuffer@0 {
			compatible = "simple-framebuffer";
			power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>,
					<&k3_pds 243 TI_SCI_PD_EXCLUSIVE>,	/* OLDI0 */
					<&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;	/* OLDI1 */
			clocks = <&k3_clks 186 6>,
				 <&dss0_vp1_clk>,
				 <&k3_clks 186 2>;
			display = <&dss0>;
			status = "disabled";
		};
	};

	opp-table {
		/* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-microvolt = <850000 850000 850000>;
			opp-supported-hw = <0x01 0x0004>;
			clock-latency-ns = <6000000>;
		};
	};

	memory@80000000 {
		bootph-pre-ram;
		device_type = "memory";

		/* 2G RAM, will be updated by dram_init_banksize and fdtdec_setup_memory_banksize */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x24000000>;
			linux,cma-default;
		};

		rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b500000 0x00 0x00300000>;
			no-map;
		};

		mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b800000 0x00 0x00100000>;
			no-map;
		};

		mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9b900000 0x00 0x00f00000>;
			no-map;
		};

		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c800000 0x00 0x00100000>;
			no-map;
		};

		wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0x9c900000 0x00 0x01e00000>;
			no-map;
		};

		secure_tfa_ddr: tfa@9e780000 {
			reg = <0x00 0x9e780000 0x00 0x80000>;
			no-map;
		};

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			no-map;
		};
	};

	som_vdd_3v3: som_vdd_3v3 {
		/* 3.3V VDD Enable of AP22653AW6 - Pin 21 on SOM */
		compatible = "regulator-fixed";
		regulator-name = "som_vdd_3v3_enable";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vin_3v3_som>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
	};

	som_vdd_1v8: som_vdd_1v8 {
		/* 1.8V VDD Output of TPS65219 */
		compatible = "regulator-fixed";
		regulator-name = "som_vdd_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		// vin-supply = <&buck2>;
		regulator-always-on;
		regulator-boot-on;
	};

	som_led {
		compatible = "gpio-leds";
		led-0 {
			label = "som-d1";
			function = LED_FUNCTION_DEBUG;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&main_gpio0 1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "none";
			default-state = "off";
		};
	};
};

/* Ensure we wait for pmic driver to probe before cpufreq */
&cpu0 {
	cpu-supply = <&buck12>;
};

&cpu1 {
	cpu-supply = <&buck12>;
};

&cpu2 {
	cpu-supply = <&buck12>;
};

&cpu3 {
	cpu-supply = <&buck12>;
};

&main_pmx0 {
	bootph-all;

	main_uart0_pins_default: main-uart0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x1c8, PIN_INPUT, 0)	/* (A22) UART0_RXD */
			AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0)	/* (B22) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */
			AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */
			AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */
			AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */
		>;
	};

	main_i2c0_pins_default: main-i2c0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */
			AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */
		>;
	};

	main_mmc0_pins_default: main-mmc0-default-pins {
		bootph-all;
	};


	ospi0_pins_default: ospi0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */
			AM62PX_IOPAD(0x02c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */
			AM62PX_IOPAD(0x00c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */
			AM62PX_IOPAD(0x010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */
			AM62PX_IOPAD(0x014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */
			AM62PX_IOPAD(0x018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */
			AM62PX_IOPAD(0x01c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */
			AM62PX_IOPAD(0x020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */
			AM62PX_IOPAD(0x024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */
			AM62PX_IOPAD(0x028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */
			AM62PX_IOPAD(0x008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */
			AM62PX_IOPAD(0x0034, PIN_INPUT_PULLUP, 7) /* (L22) OSPI0_CSn2.GPIO0_13 SOM:OSPI_INTn_0 NC(R42) external pullup */
			AM62PX_IOPAD(0x0038, PIN_INPUT_PULLUP, 7) /* (L23) OSPI0_CSn3.GPIO0_14 SOM:OSPI_RESET_GPIO external pullup */
		>;
	};

	som_usb0_pins_default: som-usb0-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0254, PIN_INPUT, 0) /* (G22) USB0_DRVVBUS */
		>;
	};

	som_usb1_pins_default: som-usb1-default-pins {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */
		>;
	};

	som_pmic_int_pins_default: som_pmic_int_pins_default {
		pinctrl-single,pins = <
			AM62PX_IOPAD(0x01f4, PIN_INPUT, 7) /* (C23) EXTINTn.GPIO1_31 SOM:Pullup */
		>;
	};
};

&mcu_pmx0 {
	bootph-all;
	pinctrl-names = "default";
	pinctrl-0 = <&som_mcu_system_pins_default>;

	som_mcu_system_pins_default: mcu_system_pins_default {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x0058, PIN_INPUT, 0) /* (H6) MCU_PORz */
			AM62PX_MCU_IOPAD(0x0060, PIN_INPUT_PULLDOWN, 0) /* (G6) MCU_ERRORn */
			AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F14) WKUP_CLKOUT0 TP10 */
			AM62PX_MCU_IOPAD(0x0080, PIN_OUTPUT, 0) /* (B9) MCU_RESETz */
		>;
	};

	wkup_uart0_pins_default: wkup-uart0-default-pins {
		bootph-all;
		pinctrl-single,pins = <
			AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0)	/* (D8) WKUP_UART0_RXD */
			AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
		>;
	};
};

&wkup_uart0 {
	bootph-all;
	/* WKUP UART0 is used by DM firmware */
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
};

&main_uart0 {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	interrupts-extended = <&gic500 GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			       <&main_pmx0 0x1c8>; /* (D14) UART0_RXD PADCONFIG114 */
	interrupt-names = "irq", "wakeup";
};

&main_uart1 {
	/* Main UART1 is used by TIFS firmware */
	bootph-all;
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	tps65224: pmic@48 {
		compatible = "ti,tps65224-q1";
		status = "okay";
		reg = <0x48>;

		pinctrl-names = "default";
		pinctrl-0 = <&som_pmic_int_pins_default>;

		interrupt-parent = <&main_gpio1>;
		#interrupt-cells = <1>;
		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		ti,primary-pmic;

		/* Power off SOM on linux power down */
		system-power-controller;

		gpio-controller;
		#gpio-cells = <2>;

		buck12-supply = <&vin_3v3_som>;
		buck3-supply = <&vin_3v3_som>;
		buck4-supply = <&vin_3v3_som>;

		ldo1-supply = <&vin_3v3_som>;
		ldo2-supply = <&vin_3v3_som>;
		ldo3-supply = <&buck3>;

		regulators {
			buck12: buck12 {
				regulator-name = "vcc_core_buck12";
				/* Do not set min max so that this regulator becomes read only */
				/* regulator-min-microvolt = <715000>; */
				/* regulator-max-microvolt = <895000>; */
				regulator-boot-on;
				regulator-always-on;
			};

			buck3: buck3 {
				regulator-name = "vcc1v8_sys_buck3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4: buck4 {
				regulator-name = "vcc1v1_buck4";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: ldo1 {
				regulator-name = "vdda1v8_ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: ldo2 {
				regulator-name = "dvdd3v3_ldo2";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: ldo3 {
				regulator-name = "vcc_0v85_ldo3";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	/* 0x50 EEPROM */
	factory-config@50 {
		compatible = "microchip,24c32", "atmel,24c32";
		reg = <0x50>;
		pagesize = <32>;
		read-only;
	};
};

/* eMMC */
&sdhci0 {
	status = "okay";
	ti,driver-strength-ohm = <50>;
	disable-wp;
	bootph-all;
};

&fss {
	bootph-all;
};

&ospi0 {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;
};

&mailbox0_cluster0 {
	mbox_r5_0: mbox-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&mailbox0_cluster1 {
	mbox_mcu_r5_0: mbox-mcu-r5-0 {
		ti,mbox-rx = <0 0 0>;
		ti,mbox-tx = <1 0 0>;
	};
};

&wkup_r5fss0 {
	status = "okay";
};

&wkup_r5fss0_core0 {
	mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
			<&wkup_r5fss0_core0_memory_region>;
};

&mcu_r5fss0 {
	status = "okay";
};

&mcu_r5fss0_core0 {
	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
			<&mcu_r5fss0_core0_memory_region>;
};

&main_gpio0 {
	bootph-all;
	gpio-line-names = "GPIO0_0", "SOM_LED_D1", "GPIO0_2", "GPIO0_3",
			"GPIO0_4", "GPIO0_5", "GPIO0_6", "GPIO0_7",
			"GPIO0_8", "GPIO0_9", "GPIO0_10", "GPIO0_11",
			"GPIO0_12", "GPIO0_13", "GPIO0_14", "GPIO0_15",
			"GPIO0_16", "GPIO0_17", "GPIO0_18", "GPIO0_19",
			"GPIO0_20", "GPIO0_21", "GPIO0_22", "GPIO0_23",
			"GPIO0_24", "GPIO0_25", "GPIO0_26", "GPIO0_27",
			"GPIO0_28", "GPIO0_29", "GPIO0_30", "GPIO0_31",
			"GPIO0_32", "GPIO0_33", "GPIO0_34", "GPIO0_35",
			"GPIO0_36", "GPIO0_37", "GPIO0_38", "GPIO0_39",
			"GPIO0_40", "GPIO0_41", "GPIO0_42", "GPIO0_43",
			"GPIO0_44", "GPIO0_45", "GPIO0_46", "GPIO0_47",
			"GPIO0_48", "GPIO0_49", "GPIO0_50", "GPIO0_51",
			"GPIO0_52", "GPIO0_53", "GPIO0_54", "GPIO0_55",
			"GPIO0_56", "GPIO0_57", "GPIO0_58", "GPIO0_59",
			"GPIO0_60", "GPIO0_61", "GPIO0_62", "GPIO0_63",
			"GPIO0_64", "GPIO0_65", "GPIO0_66", "GPIO0_67",
			"GPIO0_68", "GPIO0_69", "GPIO0_70", "GPIO0_71",
			"GPIO0_72", "GPIO0_73", "GPIO0_74", "GPIO0_75",
			"GPIO0_76", "GPIO0_77", "GPIO0_78", "GPIO0_79",
			"GPIO0_80", "GPIO0_81", "GPIO0_82", "GPIO0_83",
			"GPIO0_84", "GPIO0_85", "GPIO0_86", "GPIO0_87",
			"GPIO0_88", "GPIO0_89", "GPIO0_90", "GPIO0_91";
};

&main_gpio1 {
	bootph-all;
	gpio-line-names = "GPIO1_0", "GPIO1_1", "GPIO1_2", "GPIO1_3",
			"GPIO1_4", "GPIO1_5", "GPIO1_6", "GPIO1_7",
			"GPIO1_8", "GPIO1_9", "GPIO1_10", "GPIO1_11",
			"GPIO1_12", "GPIO1_13", "GPIO1_14", "GPIO1_15",
			"GPIO1_16", "GPIO1_17", "GPIO1_18", "GPIO1_19",
			"GPIO1_20", "GPIO1_21", "GPIO1_22", "GPIO1_23",
			"GPIO1_24", "GPIO1_25", "GPIO1_26", "GPIO1_27",
			"GPIO1_28", "GPIO1_29", "GPIO1_30", "GPIO1_31",
			"GPIO1_32", "GPIO1_33", "GPIO1_34", "GPIO1_35",
			"GPIO1_36", "GPIO1_37", "GPIO1_38", "GPIO1_39",
			"GPIO1_40", "GPIO1_41", "GPIO1_42", "GPIO1_43",
			"GPIO1_44", "GPIO1_45", "GPIO1_46", "GPIO1_47",
			"GPIO1_48", "GPIO1_49", "GPIO1_50", "GPIO1_51";
};

&mcu_gpio0 {
	bootph-all;
	gpio-line-names = "MCU_GPIO0_0", "MCU_GPIO0_1", "MCU_GPIO0_2", "MCU_GPIO0_3",
			"MCU_GPIO0_4", "MCU_GPIO0_5", "MCU_GPIO0_6", "MCU_GPIO0_7",
			"MCU_GPIO0_8", "MCU_GPIO0_9", "MCU_GPIO0_10", "MCU_GPIO0_11",
			"MCU_GPIO0_12", "MCU_GPIO0_13", "MCU_GPIO0_14", "MCU_GPIO0_15",
			"MCU_GPIO0_16", "MCU_GPIO0_17", "MCU_GPIO0_18", "MCU_GPIO0_19",
			"MCU_GPIO0_20", "MCU_GPIO0_21", "MCU_GPIO0_22", "MCU_GPIO0_23";
};

We are using afy15203b from Orient Display, which is being driven by a Himax HX8394-F 720x1280 DSI to TFT Mobile Chip driver.  I updated existing panel driver file, panel-himax-hx8394.c, to support that display.  The timings and initialization code were lifted from our 335x design output and bridge chip configuration (which works) and those came from instructions from orient display.  The only difference is that we were using burst mode in the original design, and it does not appear to be supported by the current driver from Cadence (even though the TRM says it should be supported).

Here is the updated file.

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for panels based on Himax HX8394 controller, such as:
 *
 * - HannStar HSD060BHW4 5.99" MIPI-DSI panel
 *
 * Copyright (C) 2021 Kamil Trzciński
 *
 * Based on drivers/gpu/drm/panel/panel-sitronix-st7703.c
 * Copyright (C) Purism SPC 2019
 */

#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/media-bus-format.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>

#include <video/mipi_display.h>

#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>

#define DRV_NAME "panel-himax-hx8394"

/* Manufacturer specific commands sent via DSI, listed in HX8394-F datasheet */
#define HX8394_CMD_SETSEQUENCE	  0xb0
#define HX8394_CMD_SETPOWER	  0xb1
#define HX8394_CMD_SETDISP	  0xb2
#define HX8394_CMD_SETCYC	  0xb4
#define HX8394_CMD_SETVCOM	  0xb6
#define HX8394_CMD_SETTE	  0xb7
#define HX8394_CMD_SETSENSOR	  0xb8
#define HX8394_CMD_SETEXTC	  0xb9
#define HX8394_CMD_SETMIPI	  0xba
#define HX8394_CMD_SETOTP	  0xbb
#define HX8394_CMD_SETREGBANK	  0xbd
#define HX8394_CMD_UNKNOWN1	  0xc0
#define HX8394_CMD_SETDGCLUT	  0xc1
#define HX8394_CMD_SETID	  0xc3
#define HX8394_CMD_SETDDB	  0xc4
#define HX8394_CMD_UNKNOWN2	  0xc6
#define HX8394_CMD_SETCABC	  0xc9
#define HX8394_CMD_SETCABCGAIN	  0xca
#define HX8394_CMD_SETPANEL	  0xcc
#define HX8394_CMD_SETOFFSET	  0xd2
#define HX8394_CMD_SETGIP0	  0xd3
#define HX8394_CMD_UNKNOWN3	  0xd4
#define HX8394_CMD_SETGIP1	  0xd5
#define HX8394_CMD_SETGIP2	  0xd6
#define HX8394_CMD_SETGPO	  0xd6
#define HX8394_CMD_UNKNOWN4   0xd8
#define HX8394_CMD_SETSCALING	  0xdd
#define HX8394_CMD_SETIDLE	  0xdf
#define HX8394_CMD_SETGAMMA	  0xe0
#define HX8394_CMD_SETCHEMODE_DYN 0xe4
#define HX8394_CMD_SETCHE	  0xe5
#define HX8394_CMD_SETCESEL	  0xe6
#define HX8394_CMD_SET_SP_CMD	  0xe9
#define HX8394_CMD_SETREADINDEX	  0xfe
#define HX8394_CMD_GETSPIREAD	  0xff

struct hx8394 {
	struct device *dev;
	struct drm_panel panel;
	struct gpio_desc *reset_gpio;
	struct regulator *vcc;
	struct regulator *iovcc;

	const struct hx8394_panel_desc *desc;
};

struct hx8394_panel_desc {
	const struct drm_display_mode *mode;
	unsigned int lanes;
	unsigned long mode_flags;
	enum mipi_dsi_pixel_format format;
	int (*init_sequence)(struct hx8394 *ctx);
};

static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
{
	return container_of(panel, struct hx8394, panel);
}

static int afy15203b_init_sequence(struct hx8394 *ctx)
{
	char buf[4];
	ssize_t ret;
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);

	msleep(150);

	/* fetch ID of Panel.  Try twice in case junk from power on.*/
	for (int i = 0; i < 2; ++i)
	{

		msleep(2);

		mipi_dsi_set_maximum_return_packet_size(dsi,4);
	
		ret = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_ID, buf, sizeof(buf));
		if (ret < 0)
			dev_err(ctx->dev, "error fetching display panel ID (%ld)\n", ret);
		else {
			unsigned int disp_id;
			disp_id = (buf[0] & 0xFF) << 16;
			disp_id |= (buf[1] & 0xFF) << 8;
			disp_id |= (buf[2] & 0xFF);
			dev_info(ctx->dev, "Display Panel ID len (%ld) was 0x%02X%02X%02X\n", ret, buf[0], buf[1], buf[2]);
			if (disp_id != 0x0083940F)
			{
				dev_err(ctx->dev, "Invalid Panel ID Found (0x%08X)\n", disp_id);
			}
		}
	}

	/* 5.19.8 SETEXTC: Set extension command (B9h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
			       0xff, 0x83, 0x94);

	/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
		0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);

		/* 5.19.2 SETPOWER: Set power (B1h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
			       0x50, 0x12, 0x72, 0x09, 0x33, 0x54, 0xB1, 0x31, 0x6B, 0x2F);

	/* 5.19.3 SETDISP: Set display related register (B2h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
			       0x00, 0x80, 0x64, 0x0E, 0x0D, 0x2F /* enable these for test pattern , 0x00, 0x00, 0x00, 0x00, 0x48 */);

	/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
//			         73    74    73    74    73    74    01    0C    86    75    00    3F 
			       0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86, 0x75, 0x00, 0x3F,
//				     73    74    73    74    73    74    01    0C    86
			       0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0C, 0x86);

	/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
			       0x73,	/* Forward scan VCOM voltage control. (0x77: -1.49V, flk=8%) */
			       0x73);	/* Backward scan VCOM voltage control. */

	/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
//			         00    00    07    07    40    07    10    00    08    10
			       0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x10, 0x00, 0x08, 0x10,
//				     08    00    08    54    15    0E    05    0E    02    15
			       0x08, 0x00, 0x08, 0x54, 0x15, 0x0E, 0x05, 0x0E, 0x02, 0x15,
//				     06    05    06    47    44    0A    0A    4B    10    07
			       0x06, 0x05, 0x06, 0x47, 0x44, 0x0A, 0x0A, 0x4B, 0x10, 0x07,
//				    07     0E    40
			       0x07, 0x0E, 0x40);

	/* 5.19.20 Set GIP Option1 (D5h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
//			         1A    1A    1B    1B    00    01    02    03
			       0x1A, 0x1A, 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03,
//				     04    05    06    07    08    09    0A    0B
			       0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
//				     24    25    18    18    26    27    18    18 
			       0x24, 0x25, 0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
//				     18    18    18    18    18    18    18    18
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
//				     18    18    18    18    18    18    20    21
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
//				     18    18    18    18
				   0x18, 0x18, 0x18, 0x18);

	/* 5.19.21 Set GIP Option2 (D6h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
//			         1A    1A    1B    1B    0B    0A    09    08
			       0x1A, 0x1A, 0x1B, 0x1B, 0x0B, 0x0A, 0x09, 0x08,
//				     07    06    05    04    03    02    01    00
			       0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
//				     21    20    18    18    27    26    18    18
			       0x21, 0x20, 0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
//				     18    18    18    18    18    18    18    18
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
//				     18    18    18    18    18    18    25    24
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,
//				     18    18    18    18
			       0x18, 0x18, 0x18, 0x18);


	/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
			       0x00, 0x0C, 0x19, 0x20, 0x23, 0x26, 0x29, 0x28,
			       0x51, 0x61, 0x70, 0x6F, 0x76, 0x86, 0x89, 0x8D,
			       0x99, 0x9A, 0x95, 0xA1, 0xB0, 0x57, 0x55, 0x58,
			       0x5C, 0x5E, 0x64, 0x6B, 0x7F, 0x00, 0x0C, 0x18,
			       0x20, 0x23, 0x26, 0x29, 0x28, 0x51, 0x61, 0x70,
			       0x6F, 0x76, 0x86, 0x89, 0x8D, 0x99, 0x9A, 0x95,
			       0xA1, 0xB0, 0x57, 0x55, 0x58, 0x5C, 0x5E, 0x64,
			       0x6B, 0x7F);

	/* Unknown command (C0h), not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
			       0x1f, 0x31 /* 0x73 */);

	/* CABC Control1 (C9h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC,
			       0x76, 0x00, 0x30);

	/* 5.19.17 SETPANEL (CCh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
			       0x03);

	/* Unknown command (D4h), not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
			       0x02);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
			       0x02);

	/* Unknown command (D8h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
			       0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
			       0xFF, 0xFF, 0xFF);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
		0x00);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
		0x01);

	/* 5.19.2 SETPOWER: Set power (B1h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
			       0x00);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
			       0x00);

	/* Unknown command (C6H), not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
			       0xED /* 0xEF */);

    /* Pixel format 24 bit or 16 bit is supported  (3Ah)*/
	mipi_dsi_dcs_set_pixel_format(dsi,  MIPI_DCS_PIXEL_FMT_24BIT  /* MIPI_DCS_PIXEL_FMT_16BIT */);

	return 0;
}

static const struct drm_display_mode afy15203b_mode = {
	.hdisplay    = 720,
	.hsync_start = 720 + 18,
	.hsync_end   = 720 + 18 + 36,
	.htotal	     = 720 + 18 + 36 + 18,
	.vdisplay    = 1280,
	.vsync_start = 1280 + 15,
	.vsync_end   = 1280 + 15 + 4,
	.vtotal	     = 1280 + 15 + 4 + 12,
	.clock	     = ( 720 + 18 + 36 + 18) * (1280 + 15 + 4 + 12) * 60 / 1000, // total / frame pixel clock in KHZ?
	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
	.width_mm    = 62,
	.height_mm   = 110,
};

static const struct hx8394_panel_desc afy15203b_desc = {
	.mode = &afy15203b_mode,
	.lanes = 4,
	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_SYNC_PULSE /* MIPI_DSI_MODE_VIDEO_BURST  MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_BURST -- not supported by TI's DSI driver*/, 
	.format = MIPI_DSI_FMT_RGB888, /*  MIPI_DSI_FMT_RGB565, */
	.init_sequence = afy15203b_init_sequence,
};

static int hsd060bhw4_init_sequence(struct hx8394 *ctx)
{
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);

	/* 5.19.8 SETEXTC: Set extension command (B9h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
			       0xff, 0x83, 0x94);

	/* 5.19.2 SETPOWER: Set power (B1h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
			       0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30);

	/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
			       0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);

	/* 5.19.3 SETDISP: Set display related register (B2h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
			       0x00, 0x80, 0x78, 0x0c, 0x07);

	/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
			       0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55,
			       0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c,
			       0x7c);

	/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
			       0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10,
			       0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00,
			       0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00,
			       0x00, 0x0c, 0x40);

	/* 5.19.20 Set GIP Option1 (D5h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
			       0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01,
			       0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18,
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
			       0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18);

	/* 5.19.21 Set GIP Option2 (D6h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
			       0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06,
			       0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18,
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
			       0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
			       0x18, 0x18, 0x18, 0x18, 0x18, 0x18);

	/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
			       0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f,
			       0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a,
			       0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00,
			       0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31,
			       0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f,
			       0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b,
			       0x4a, 0x4c, 0x4b, 0x7f);

	/* 5.19.17 SETPANEL (CCh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
			       0x0b);

	/* Unknown command, not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
			       0x1f, 0x31);

	/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
			       0x7d, 0x7d);

	/* Unknown command, not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
			       0x02);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
			       0x01);

	/* 5.19.2 SETPOWER: Set power (B1h) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
			       0x00);

	/* 5.19.11 Set register bank (BDh) */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
			       0x00);

	/* Unknown command, not listed in the HX8394-F datasheet */
	mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
			       0xed);

	return 0;
}

static const struct drm_display_mode hsd060bhw4_mode = {
	.hdisplay    = 720,
	.hsync_start = 720 + 40,
	.hsync_end   = 720 + 40 + 46,
	.htotal	     = 720 + 40 + 46 + 40,
	.vdisplay    = 1440,
	.vsync_start = 1440 + 9,
	.vsync_end   = 1440 + 9 + 7,
	.vtotal	     = 1440 + 9 + 7 + 7,
	.clock	     = 74250,
	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
	.width_mm    = 68,
	.height_mm   = 136,
};

static const struct hx8394_panel_desc hsd060bhw4_desc = {
	.mode = &hsd060bhw4_mode,
	.lanes = 4,
	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
	.format = MIPI_DSI_FMT_RGB888,
	.init_sequence = hsd060bhw4_init_sequence,
};

static int hx8394_enable(struct drm_panel *panel)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
	int ret;

	ret = ctx->desc->init_sequence(ctx);
	if (ret) {
		dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
		return ret;
	}

	msleep(20);

	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
	if (ret) {
		dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
		return ret;
	}

	msleep(120);

	ret = mipi_dsi_dcs_set_display_on(dsi);
	if (ret) {
		dev_err(ctx->dev, "Failed to turn on the display: %d\n", ret);
		goto sleep_in;
	}

	return 0;

sleep_in:
	/* This will probably fail, but let's try orderly power off anyway. */
	if (!mipi_dsi_dcs_enter_sleep_mode(dsi))
		msleep(50);

	return ret;
}

static int hx8394_disable(struct drm_panel *panel)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
	int ret;

	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
	if (ret) {
		dev_err(ctx->dev, "Failed to sleep display: %d\n", ret);
		return ret;
	}

	msleep(50); /* about 3 frames */

	return 0;
}

static int hx8394_unprepare(struct drm_panel *panel)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);

	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	regulator_disable(ctx->iovcc);
	regulator_disable(ctx->vcc);

	return 0;
}

static int hx8394_prepare(struct drm_panel *panel)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);
	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
	int ret;

	gpiod_set_value_cansleep(ctx->reset_gpio, 1);

	ret = regulator_enable(ctx->vcc);
	if (ret) {
		dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
		return ret;
	}

	ret = regulator_enable(ctx->iovcc);
	if (ret) {
		dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
		goto disable_vcc;
	}

	gpiod_set_value_cansleep(ctx->reset_gpio, 0);

	msleep(180);

	return 0;

disable_vcc:
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	regulator_disable(ctx->vcc);
	return ret;
}

static int hx8394_get_modes(struct drm_panel *panel,
			    struct drm_connector *connector)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);
	struct drm_display_mode *mode;

	mode = drm_mode_duplicate(connector->dev, ctx->desc->mode);
	if (!mode) {
		dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
			ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
			drm_mode_vrefresh(ctx->desc->mode));
		return -ENOMEM;
	}

	drm_mode_set_name(mode);

	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
	connector->display_info.bpc = 8;
	connector->display_info.width_mm = mode->width_mm;
	connector->display_info.height_mm = mode->height_mm;
	drm_mode_probed_add(connector, mode);

	drm_connector_set_panel_orientation(connector, 0);

	return 1;
}

static enum drm_panel_orientation hx8394_get_orientation(struct drm_panel *panel)
{
	struct hx8394 *ctx = panel_to_hx8394(panel);

	return 0;
}

static const struct drm_panel_funcs hx8394_drm_funcs = {
	.disable   = hx8394_disable,
	.unprepare = hx8394_unprepare,
	.prepare   = hx8394_prepare,
	.enable	   = hx8394_enable,
	.get_modes = hx8394_get_modes,
	.get_orientation = hx8394_get_orientation,
};

static int hx8394_probe(struct mipi_dsi_device *dsi)
{
	struct device *dev = &dsi->dev;
	struct hx8394 *ctx;
	int ret;

	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return -ENOMEM;

	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
	if (IS_ERR(ctx->reset_gpio))
		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
				     "Failed to get reset gpio\n");

	mipi_dsi_set_drvdata(dsi, ctx);

	ctx->dev = dev;
	ctx->desc = of_device_get_match_data(dev);

	dsi->mode_flags = ctx->desc->mode_flags;
	dsi->format = ctx->desc->format;
	dsi->lanes = ctx->desc->lanes;

	ctx->vcc = devm_regulator_get(dev, "vcc");
	if (IS_ERR(ctx->vcc))
		return dev_err_probe(dev, PTR_ERR(ctx->vcc),
				     "Failed to request vcc regulator\n");

	ctx->iovcc = devm_regulator_get(dev, "iovcc");
	if (IS_ERR(ctx->iovcc))
		return dev_err_probe(dev, PTR_ERR(ctx->iovcc),
				     "Failed to request iovcc regulator\n");

	drm_panel_init(&ctx->panel, dev, &hx8394_drm_funcs,
		       DRM_MODE_CONNECTOR_DSI);

	ret = drm_panel_of_backlight(&ctx->panel);
	if (ret)
		return ret;

	drm_panel_add(&ctx->panel);

	ret = mipi_dsi_attach(dsi);
	if (ret < 0) {
		dev_err_probe(dev, ret, "mipi_dsi_attach failed\n");
		drm_panel_remove(&ctx->panel);
		return ret;
	}

	dev_dbg(dev, "%ux%u@%u %ubpp dsi %udl - ready\n",
		ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
		drm_mode_vrefresh(ctx->desc->mode),
		mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);

	return 0;
}

static void hx8394_shutdown(struct mipi_dsi_device *dsi)
{
	struct hx8394 *ctx = mipi_dsi_get_drvdata(dsi);
	int ret;

	ret = drm_panel_disable(&ctx->panel);
	if (ret < 0)
		dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);

	ret = drm_panel_unprepare(&ctx->panel);
	if (ret < 0)
		dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
}

static void hx8394_remove(struct mipi_dsi_device *dsi)
{
	struct hx8394 *ctx = mipi_dsi_get_drvdata(dsi);
	int ret;

	hx8394_shutdown(dsi);

	ret = mipi_dsi_detach(dsi);
	if (ret < 0)
		dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);

	drm_panel_remove(&ctx->panel);
}

static const struct of_device_id hx8394_of_match[] = {
	{ .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
	{ .compatible = "orientdisplay,afy15203b", .data = &afy15203b_desc },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, hx8394_of_match);

static struct mipi_dsi_driver hx8394_driver = {
	.probe	= hx8394_probe,
	.remove = hx8394_remove,
	.shutdown = hx8394_shutdown,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = hx8394_of_match,
	},
};
module_mipi_dsi_driver(hx8394_driver);

MODULE_AUTHOR("Kamil Trzciński <ayufan@ayufan.eu>");
MODULE_DESCRIPTION("DRM driver for Himax HX8394 based MIPI DSI panels");
MODULE_LICENSE("GPL");

I can provide datasheets, etc. for the panel.  But I can't see how to attach files here.  Send me a way to send PDFs and I will supply them.

We have tried on a separate branch to incorporate the other drm changes you pointed to, but the behavior was the same, so it's not clear if that really helped or not, and I'd rather work from your released TI SDK if possible.

I am also open to checking the hardware design.  But, given we can control the panel over the LPM on channel 0 and put the panel into test mode, I don't think anything is wrong with the connections.  My only thought might be is there is a PLL or something in the 62P that isn't locking because of a rail or something.  But I need help to isolate that kind of issue.

Please let me know if you need additional information.

We don't have anything in the pipeline, just trying to run the base TI weston / startup application.

kernel DSI and DSS messages:

root@mitysom-am62px:~# dmesg | grep -e dss -e dsi -e drm -e mipi -e max
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.023929] pid_max: default: 32768 minimum: 301
[    0.256810] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.398961] /bus@f0000/dss@30220000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    0.407519] /bus@f0000/dsi@30500000: Fixed dependency cycle(s) with /bus@f0000/dss@30220000
[    0.416060] /bus@f0000/dsi@30500000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000/panel-dsi@0
[    0.425675] /bus@f0000/dsi@30500000/panel-dsi@0: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    0.531735] /bus@f0000/dss@30220000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    0.540530] /bus@f0000/dss@30220000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    0.549118] /bus@f0000/dsi@30500000: Fixed dependency cycle(s) with /bus@f0000/dss@30220000
[    0.557710] /bus@f0000/dsi@30500000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000/panel-dsi@0
[    0.567380] /bus@f0000/dsi@30500000/panel-dsi@0: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    0.900346] workingset: timestamp_bits=46 max_order=19 bucket_order=0
[    3.800212] systemd[1]: Starting Load Kernel Module drm...
[    6.989971] /bus@f0000/dsi@30500000: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000/panel-dsi@0
[    7.026393] /bus@f0000/dsi@30500000/panel-dsi@0: Fixed dependency cycle(s) with /bus@f0000/dsi@30500000
[    7.321531] OF: graph: no port node found in /bus@f0000/dss@30200000/oldi-txes/oldi@0/ports
[    7.330596] OF: graph: no port node found in /bus@f0000/dss@30200000/oldi-txes/oldi@1/ports
[    7.369111] [drm] Initialized tidss 1.0.0 20180215 for 30200000.dss on minor 0
[    7.380862] tidss 30200000.dss: [drm] No compatible format found
[    7.390903] tidss 30200000.dss: [drm] Cannot find any crtc or sizes
[    7.463044] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    7.637980] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    7.707501] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    7.853103] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    7.969531] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.011507] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.061226] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.150329] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.171208] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.614593] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.674379] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.719567] OF: graph: no port node found in /bus@f0000/dss@30220000/oldi-txes/oldi@1/ports
[    8.731365] [drm] Initialized tidss 1.0.0 20180215 for 30220000.dss on minor 1
[    9.403430] panel-himax-hx8394 30500000.dsi.0: Display Panel ID len (0) was 0x000000
[    9.403462] panel-himax-hx8394 30500000.dsi.0: Invalid Panel ID Found (0x00000000)
[    9.418145] panel-himax-hx8394 30500000.dsi.0: Display Panel ID len (0) was 0x83940F
[    9.711581] tidss 30220000.dss: [drm] fb0: tidssdrmfb frame buffer device
[   42.375285] panel-himax-hx8394 30500000.dsi.0: Display Panel ID len (0) was 0x83940F
[   42.394076] panel-himax-hx8394 30500000.dsi.0: Display Panel ID len (0) was 0x83940F

Thanks Michael.

Michael Williamson said:

But I can't see how to attach files here.  Send me a way to send PDFs and I will supply them.

You can simply drag and drop the pdf into the reply box here to attach it.

Ok.

The datasheets are marked confidential/proprietary with "do not copy" watermarks so I can't post them here.

The timings called out in the datasheets are in the panel timings structure in the panel-himax-hx8394.c file I provided.  If you need additional information let me know and I will try to get permission to post what is required.

With regards,

Mike

That works too, thanks.
I have created a ticket with Cadence and will keep you updated as and when we receive further debug feedback.

Hi,
Another question: Does your panel support touchscreen input? If so, can you check using  evtest utility if the touchscreen functionality works?

I have not worked on integrating the touch panel controller.  The i2c device controller for it shows up, but I haven't added it to the device tree or enabled the drivers.  We haven't really been concerned about the touch panel controller as we have existing AM62x designs with panels using a controller from the same I2C family / manufacturer.

If you think there is value in this I can enable the driver and try to run an evtest (not sure how to skip the TS calibation cycle that the OS usually runs on a new touch device being identified).

I retested this panel on the original 335x board (it still works) and tried a second (same behavior).

Hello.

To follow up.  I am able to get touch events using "evtest /dev/input/touchscreen0".  If you want any specific test done or would like to see additional logs, let me know.

root@mitysom-am62px:~# evtest /dev/input/touchscreen0 
Input driver version is 1.0.1
Input device ID: bus 0x18 vendor 0x0 product 0x0 version 0x0
Input device name: "1-0038 EP0570M09"
Supported events:
  Event type 0 (EV_SYN)
  Event type 1 (EV_KEY)
    Event code 330 (BTN_TOUCH)
  Event type 3 (EV_ABS)
    Event code 0 (ABS_X)
      Value      0
      Min        0
      Max       -1
    Event code 1 (ABS_Y)
      Value      0
      Min        0
      Max       -1
    Event code 47 (ABS_MT_SLOT)
      Value      0
      Min        0
      Max        4
    Event code 53 (ABS_MT_POSITION_X)
      Value      0
      Min        0
      Max       -1
    Event code 54 (ABS_MT_POSITION_Y)
      Value      0
      Min        0
      Max       -1
    Event code 57 (ABS_MT_TRACKING_ID)
      Value      0
      Min        0
      Max    65535
Properties:
  Property type 1 (INPUT_PROP_DIRECT)
Testing ... (interrupt to exit)
Event: time 1744037815.391926, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 0
Event: time 1744037815.391926, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 617
Event: time 1744037815.391926, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 94
Event: time 1744037815.391926, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 1
Event: time 1744037815.391926, type 3 (EV_ABS), code 0 (ABS_X), value 617
Event: time 1744037815.391926, type 3 (EV_ABS), code 1 (ABS_Y), value 94
Event: time 1744037815.391926, -------------- SYN_REPORT ------------
Event: time 1744037815.488069, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 616
Event: time 1744037815.488069, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 98
Event: time 1744037815.488069, type 3 (EV_ABS), code 0 (ABS_X), value 616
Event: time 1744037815.488069, type 3 (EV_ABS), code 1 (ABS_Y), value 98
Event: time 1744037815.488069, -------------- SYN_REPORT ------------
Event: time 1744037815.497680, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
Event: time 1744037815.497680, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 0
Event: time 1744037815.497680, -------------- SYN_REPORT ------------
Event: time 1744037816.777109, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 1
Event: time 1744037816.777109, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 155
Event: time 1744037816.777109, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 1109
Event: time 1744037816.777109, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 1
Event: time 1744037816.777109, type 3 (EV_ABS), code 0 (ABS_X), value 155
Event: time 1744037816.777109, type 3 (EV_ABS), code 1 (ABS_Y), value 1109
Event: time 1744037816.777109, -------------- SYN_REPORT ------------
Event: time 1744037816.957808, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
Event: time 1744037816.957808, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 0
Event: time 1744037816.957808, -------------- SYN_REPORT ------------
Event: time 1744037817.566173, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 2
Event: time 1744037817.566173, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 644
Event: time 1744037817.566173, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 1159
Event: time 1744037817.566173, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 1
Event: time 1744037817.566173, type 3 (EV_ABS), code 0 (ABS_X), value 644
Event: time 1744037817.566173, type 3 (EV_ABS), code 1 (ABS_Y), value 1159
Event: time 1744037817.566173, -------------- SYN_REPORT ------------
Event: time 1744037817.715981, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 639
Event: time 1744037817.715981, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 1158
Event: time 1744037817.715981, type 3 (EV_ABS), code 0 (ABS_X), value 639
Event: time 1744037817.715981, type 3 (EV_ABS), code 1 (ABS_Y), value 1158
Event: time 1744037817.715981, -------------- SYN_REPORT ------------
Event: time 1744037817.725597, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
Event: time 1744037817.725597, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 0
Event: time 1744037817.725597, -------------- SYN_REPORT ------------
Event: time 1744037818.621845, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value 3
Event: time 1744037818.621845, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 144
Event: time 1744037818.621845, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 60
Event: time 1744037818.621845, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 1
Event: time 1744037818.621845, type 3 (EV_ABS), code 0 (ABS_X), value 144
Event: time 1744037818.621845, type 3 (EV_ABS), code 1 (ABS_Y), value 60
Event: time 1744037818.621845, -------------- SYN_REPORT ------------
Event: time 1744037818.707968, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 141
Event: time 1744037818.707968, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 62
Event: time 1744037818.707968, type 3 (EV_ABS), code 0 (ABS_X), value 141
Event: time 1744037818.707968, type 3 (EV_ABS), code 1 (ABS_Y), value 62
Event: time 1744037818.707968, -------------- SYN_REPORT ------------
Event: time 1744037818.718647, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 64
Event: time 1744037818.718647, type 3 (EV_ABS), code 1 (ABS_Y), value 64
Event: time 1744037818.718647, -------------- SYN_REPORT ------------
Event: time 1744037818.729338, type 3 (EV_ABS), code 53 (ABS_MT_POSITION_X), value 140
Event: time 1744037818.729338, type 3 (EV_ABS), code 0 (ABS_X), value 140
Event: time 1744037818.729338, -------------- SYN_REPORT ------------
Event: time 1744037818.740018, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 65
Event: time 1744037818.740018, type 3 (EV_ABS), code 1 (ABS_Y), value 65
Event: time 1744037818.740018, -------------- SYN_REPORT ------------
Event: time 1744037818.761371, type 3 (EV_ABS), code 54 (ABS_MT_POSITION_Y), value 66
Event: time 1744037818.761371, type 3 (EV_ABS), code 1 (ABS_Y), value 66
Event: time 1744037818.761371, -------------- SYN_REPORT ------------
Event: time 1744037818.781322, type 3 (EV_ABS), code 57 (ABS_MT_TRACKING_ID), value -1
Event: time 1744037818.781322, type 1 (EV_KEY), code 330 (BTN_TOUCH), value 0
Event: time 1744037818.781322, -------------- SYN_REPORT ------------
q
^C
root@mitysom-am62px:~# 

Thanks for testing and confirming this. This test is enough. We are yet to hear from Cadence, will keep you posted with the updates here.

Hello,

Just checking in, any feedback from Cadence or other experiments to debug this issue you'd recommend?

Thanks,

Mike

Hi Michael,
Cadence has started looking into it and they have this thread as reference to the issue. Currently we haven't received any responses, but please expect some delay. 

FYI.  We tried using the panel patch on top of the latest SDK 11 and get the same results.

Hi Michael,

Divyansh Mittal said:

There are a few patches for the cdns driver available at: https://lore.kernel.org/all/20250320-cdns-dsi-impro-v1-18-725277c5f43b@ideasonboard.com/#r.

Cadence responded with the 2 of the patches in the patch series I shared with you earlier and did not work for you.
Just to confirm, you had applied all of the patches in the given patch series?

Which 2 patches did they want (there are 18 in the set)?

I had backported those patches onto the 6.6.x kernel from SDK 10. but they did not apply clean, I had to manually merge some of them.   It didn't appear to change the behavior.  I can try it again with SDK 11 (6.6.11) today if there is value in that.

Sorry SDK 11 should have been (6.12.x) kernel.

They mentioned these patches:

OK.  I applied those specific patches on top of the SDK 11 kernel and I get the same results, with the status still reporting 0x4 instead of 0x1 like your example.

Hi,
Lets join a debug session for this. Please respond to the mail you would have received.

Michael,
Based on the debug session, please carry out the experiment mentioned under example of sequence under section: 12.9.2.7.7.4 TVG Configuration of the TRM (https://www.ti.com/lit/pdf/spruj83) and share your results.

Meanwhile, I am also conducting the same on my end.

Hi Divyansh,

OK.  I have been able to get the test pattern running with the script below.  I am able to see horizontal strips, red and green, 32 pixels per stripe, on the display when I run the script.  Note: I had to disable the VID_EN prior to enabling the TVG, then re-enable the VID_EN bit in the MAIN_DATA_CTRL as shown in the script for the output to start (see the 2 sleep commands in the script).

So it seems like the hardware is OK, and the issue must be in DPI->DSI datapath configuration (a driver issue?).  Not sure where to look now.  Perhaps we can get some guidance on interpreting the status registers.

#!/bin/bash
#!/bin/bash

# dump out existing settings
echo "DSI_VID_VSIZE1"
k3conf read 0x305000B4 | grep addr
echo "DSI_VID_VSIZE2"
k3conf read 0x305000B8 | grep addr
echo "DSI_VID_HSIZE1"
k3conf read 0x305000C0 | grep addr
echo "DSI_VID_HSIZE2"
k3conf read 0x305000C4 | grep addr
echo "DSI_VID_BLKSIZE1"
k3conf read 0x305000CC | grep addr
echo "DSI_VID_BLKSIZE2"
k3conf read 0x305000D0 | grep addr
echo "DSI_VID_PCK_TIME"
k3conf read 0x305000D8 | grep addr
echo "DSI_VID_DPHY_TIME"
k3conf read 0x305000DC | grep addr 
echo "DSI_VID_MODE_STS"
k3conf read 0x305000F0 | grep addr 
echo "DSI_VID_VCA_SETTING1"
k3conf read 0x305000F4 | grep addr 
echo "DSI_VID_VCA_SETTING2"
k3conf read 0x305000F8 | grep addr 
echo "DSI_TVG_CTL"
k3conf read 0x305000FC | grep addr 
echo "DSI_TVG_IMG_SIZE"
k3conf read 0x30500100 | grep addr 
echo "DSI_TVG_COLOR1"
k3conf read 0x30500104 | grep addr 
echo "DSI_TVG_COLOR1_BIS"
k3conf read 0x30500108 | grep addr 
echo "DSI_TVG_COLOR2"
k3conf read 0x3050010C | grep addr 
echo "DSI_TVG_COLOR2_BIS"
k3conf read 0x30500110 | grep addr 
echo "DSI_TVG_STS"
k3conf read 0x30500114 | grep addr
echo "DSI_MAIN_DATA_CTL"
k3conf read 0x30500004 | grep addr
echo "DSI_MCTL_MAIN_EN"
k3conf read 0x3050000C | grep addr

echo "-------- Enabling test pattern"
echo "DSI_TVG_CTL WRITE (disable TVG_RUN)"
k3conf write 0x305000fc 0x000000B8 | grep addr
sleep 1
echo "DSI_MCTL_MAIN_EN WRITE (disable IF2_EN)"
k3conf write 0x3050000C 0x000000F9 | grep addr 
echo "DSI_MAIN_DATA_CTL WRITE (enable TVG, disable VID_EN)"
k3conf write 0x30500004 0x00020047 | grep addr 
sleep 1
echo "DSI_MAIN_DATA_CTL WRITE (enable TVG, enable VID_EN)"
k3conf write 0x30500004 0x00020067 | grep addr 
echo "DSI_TVG_IMG_SIZE WRITE (setup lines / size 720x1280)"
k3conf write 0x30500100 0x05000870 | grep addr 
echo "TEST PATTERN COLOR 1"
k3conf write 0x30500104 0x0FFF0000 | grep addr 
k3conf write 0x30500108 0x00000000 | grep addr 
echo "TEST PATTERN COLOR 2"
k3conf write 0x3050010c 0x00000FFF | grep addr 
k3conf write 0x30500110 0x00000000 | grep addr 
echo "DSI_TVG_CTL WRITE (enable TVG_RUN)"
k3conf write 0x305000fc 0x000000B9 | grep addr 

echo "DSI_TVG_STS"
k3conf read 0x30500114 | grep addr

Results from running the script:

root@mitysom-am62px:~# ./dsi_tp 
DSI_VID_VSIZE1
Value at addr 0x305000b4 = 0xf2c5
DSI_VID_VSIZE2
Value at addr 0x305000b8 = 0x500
DSI_VID_HSIZE1
Value at addr 0x305000c0 = 0x2a005e
DSI_VID_HSIZE2
Value at addr 0x305000c4 = 0x300870
DSI_VID_BLKSIZE1
Value at addr 0x305000cc = 0x93e
DSI_VID_BLKSIZE2
Value at addr 0x305000d0 = 0x8d6
DSI_VID_PCK_TIME
Value at addr 0x305000d8 = 0x0
DSI_VID_DPHY_TIME
Value at addr 0x305000dc = 0x760239
DSI_VID_MODE_STS
Value at addr 0x305000f0 = 0x1
DSI_VID_VCA_SETTING1
Value at addr 0x305000f4 = 0x0
DSI_VID_VCA_SETTING2
Value at addr 0x305000f8 = 0x8d00000
DSI_TVG_CTL
Value at addr 0x305000fc = 0xb9
DSI_TVG_IMG_SIZE
Value at addr 0x30500100 = 0x5000870
DSI_TVG_COLOR1
Value at addr 0x30500104 = 0xff0000
DSI_TVG_COLOR1_BIS
Value at addr 0x30500108 = 0x0
DSI_TVG_COLOR2
Value at addr 0x3050010c = 0xfff
DSI_TVG_COLOR2_BIS
Value at addr 0x30500110 = 0x0
DSI_TVG_STS
Value at addr 0x30500114 = 0x1
DSI_MAIN_DATA_CTL
Value at addr 0x30500004 = 0x20067
DSI_MCTL_MAIN_EN
Value at addr 0x3050000c = 0xf9
-------- Enabling test pattern
DSI_TVG_CTL WRITE (disable TVG_RUN)
Value at addr 0x305000fc = 0xb8
DSI_MCTL_MAIN_EN WRITE (disable IF2_EN)
Value at addr 0x3050000c = 0xf9
DSI_MAIN_DATA_CTL WRITE (enable TVG, disable VID_EN)
Value at addr 0x30500004 = 0x20047
DSI_MAIN_DATA_CTL WRITE (enable TVG, enable VID_EN)
Value at addr 0x30500004 = 0x20067
DSI_TVG_IMG_SIZE WRITE (setup lines / size 720x1280)
Value at addr 0x30500100 = 0x5000870
TEST PATTERN COLOR 1
Value at addr 0x30500104 = 0xff0000
Value at addr 0x30500108 = 0x0
TEST PATTERN COLOR 2
Value at addr 0x3050010c = 0xfff
Value at addr 0x30500110 = 0x0
DSI_TVG_CTL WRITE (enable TVG_RUN)
Value at addr 0x305000fc = 0xb9
DSI_TVG_STS
Value at addr 0x30500114 = 0x1

With regards,

Mike

Thanks Michael,
This is what I see on my single channel DSI panel:

root@am62pxx-evm:~# ./dsi_test.sh
DSI_VID_VSIZE1
Value at addr 0x305000b4 = 0x3148
DSI_VID_VSIZE2
Value at addr 0x305000b8 = 0x1e0
DSI_VID_HSIZE1
Value at addr 0x305000c0 = 0xe40052
DSI_VID_HSIZE2
Value at addr 0x305000c4 = 0x8a0960
DSI_VID_BLKSIZE1
Value at addr 0x305000cc = 0xb36
DSI_VID_BLKSIZE2
Value at addr 0x305000d0 = 0xada
DSI_VID_PCK_TIME
Value at addr 0x305000d8 = 0x0
DSI_VID_DPHY_TIME
Value at addr 0x305000dc = 0x1560aea
DSI_VID_MODE_STS
Value at addr 0x305000f0 = 0x1
DSI_VID_VCA_SETTING1
Value at addr 0x305000f4 = 0x0
DSI_VID_VCA_SETTING2
Value at addr 0x305000f8 = 0xad40000
DSI_TVG_CTL
Value at addr 0x305000fc = 0x0
DSI_TVG_IMG_SIZE
Value at addr 0x30500100 = 0x0
DSI_TVG_COLOR1
Value at addr 0x30500104 = 0x0
DSI_TVG_COLOR1_BIS
Value at addr 0x30500108 = 0x0
DSI_TVG_COLOR2
Value at addr 0x3050010c = 0x0
DSI_TVG_COLOR2_BIS
Value at addr 0x30500110 = 0x0
DSI_TVG_STS
Value at addr 0x30500114 = 0x0
DSI_MAIN_DATA_CTL
Value at addr 0x30500004 = 0x20027
DSI_MCTL_MAIN_EN
Value at addr 0x3050000c = 0x4019
-------- Enabling test pattern
DSI_TVG_CTL WRITE (disable TVG_RUN)
Value at addr 0x305000fc = 0xb8
DSI_MCTL_MAIN_EN WRITE (disable IF2_EN)
Value at addr 0x3050000c = 0xf9
DSI_MAIN_DATA_CTL WRITE (enable TVG, disable VID_EN)
Value at addr 0x30500004 = 0x20047
DSI_MAIN_DATA_CTL WRITE (enable TVG, enable VID_EN)
Value at addr 0x30500004 = 0x20067
DSI_TVG_IMG_SIZE WRITE (setup lines / size 720x1280)
Value at addr 0x30500100 = 0x5000870
TEST PATTERN COLOR 1
Value at addr 0x30500104 = 0xff0000
Value at addr 0x30500108 = 0x0
TEST PATTERN COLOR 2
Value at addr 0x3050010c = 0xfff
Value at addr 0x30500110 = 0x0
DSI_TVG_CTL WRITE (enable TVG_RUN)
Value at addr 0x305000fc = 0xb9
DSI_TVG_STS
Value at addr 0x30500114 = 0x1