[FAQ] AM6442, AM6441, AM6422, AM6421, AM6412, AM6411 and AM2434, AM2432, AM2431 (ALV, ALX) Custom board hardware design – USB2.0 interface

Part Number: AM6442
Other Parts Discussed in Thread: TMDS243EVM, TMDS243DC01EVM, TMDS64DC01EVM, LP-AM243, BP-AM2BLDCSERVO, BOOSTXL-IOLINKM-8, TUSB320, AM625, AM62P-Q1, TUSB321

Hi TI Experts,

I have the below queries regarding implementation of USB interface

1. Supported USB interface configuration

2. Is VBUS connection required for Host configuration or Device configuration

3.  Can I have the VBUS supply input connected when the SoC power supply is switched off

4. Is there a power sequencing requirement for VBUS 

5. Can I connect 5V input from the USB connector directly to VBUS 

6. Recommended VBUS supply voltage divider 

7. SOC VBUS input voltage range and Zener diode connection 

8. Supported USB Backup bootmode configuration. 

9. Recommended USB RCALIB resistor 

10. How to deal with the USB unused pins 

11. Is the USB0_ID connection required for Host configuration or Device configuration.  

12. Power supply switching and protection when the SOC is configured as USB Host

13. Are these recommendations valid for other Sitara processors or MCUs? 

14. Do you have some recommendations on the Type-C implementation.

15. Can I use 3.4K instead of 3.5K.

16. Do the differential signal pins (USB, etc.) have the capabilities to adjust the swing of the voltage?

Let me know your thoughts.

  • Hi Board designers, 

    1. Supported USB interface configuration. 

    USB0 interface supports Host or Device or Dual-Role (DRD)

    1. Is the VBUS connection required for Host configuration or Device configuration.

    VBUS connection for Host interface is optional.

    It is recommended to connect the VBUS when the USB interface is configured as Device.

    The recommended voltage range is the divided voltage equivalent of 4.75 V - 5.25 V for normal operation.  

    1. Can I have the VBUS supply input connected when the SoC power supply is switched off

    USB VBUS IO is fail-safe. The VBUS input does not have any dependency on the SOC power supply.

    1. Is there a power sequencing requirement for VBUS input. 

    USB VBUS IO is fail-safe and do not have any sequencing requirements.

    1. Can I connect 5 V input from the USB connector directly to VBUS input. 

    VBUS pin cannot be connected directly to external/connector VBUS, as IO is not 5 V compliant. Recommend using voltage divider and/or current limiter to ensure IO requirements are met. VBUS pin can be consider fail-safe only if recommended external divider circuit is used.

    Connection of 3.3 V directly to VBUS input is not allowed or recommended.

    For USB Device interface, it is recommended to connect a switched external USB VBUS supply to the USB0_VBUS input of the SOC through recommended resistor divider.

    1. Recommended VBUS supply voltage divider 

    Refer section 9.2.3 USB VBUS Design Guidelines of the data sheet.

    1. SOC VBUS input voltage range and Zener diode connection 

    We do not define VBUS thresholds. VBUS thresholds are defined in the USB specification. The thresholds were designed to be compliant to the USB specifications and validated via USB-IF compliance tests.
    The VBUS input has an ESD clamp to the 3.3 V rail. The USB VBUS Design Guidelines section of the datasheet defines the VBUS connection topology. This voltage divider / clamp circuit allows VBUS to go up to 30 V without harming the VBUS input. The Zener diode could be removed and a 20 KΩ resistor could be substituted for the 16.5 KΩ and 3.5 KΩ resistors if your system will never apply a VBUS potential greater than 5.5 V and the 5.5 V is sourced on-board.

    1. Supported USB Backup bootmode configuration.

    USB0 interface is recommended to be configured as a device. USB DFU backup mode works with 0.75 V SOC core supply.

    1. Recommended USB RCALIB resistor 

    Refer below section of the data sheet. 

    6.3.25 USB, 6.3.25.1 MAIN Domain, Table 6-79. USB0 Signal Descriptions

    RCALIB resistor should not exceed ±1% at any operating condition for the lifetime of the product.

    1. How to deal with the USB unused pins 

    Refer below section of the data sheet. 

    6.4 Pin Connectivity Requirements, Table 6-80. Connectivity Requirements 

    1. Is the USB0_ID connection required for Host configuration or Device configuration. 

    It is recommended to connect USB0_ID pin to VSS through a 0 Ω resistor when the USB interface is configured as Host.

    It is recommended to leave the USB0_ID pin floating when the USB interface is configured as Device.

    For implementations that do require DRD functionality, connect USB0_ID pin directly to the corresponding ID pin on a USB Micro-AB connector. Depending on the cable attached, the USB0_ID pin will be terminated, and the processor will be configured as Host or Device.

    1. Power supply switching and protection when the SOC is configured as USB Host

    USB0_DRVVBUS can be used to control the power (load) switch. The USB interface or the Linux driver is not checking the status of VBUS to determine if there is a fault condition. In that case, you should connect the fault output of the VBUS power (load) switch to a GPIO and configure the GPIO to generate an interrupt that indicates there has been an over-current condition.

    1. Are these recommendations valid for other Sitara processors or MCUs?

    The recommendations are valid for the following family of devices:

    AM243x

    1. Do you have some recommendations on the Type-C implementation.

      AM64x EVM or SK does not have the implementation.

      Refer below starter kit for implementation.

      https://www.ti.com/tool/SK-AM62B-P1

    2. Can I use 3.4K instead of 3.5K.

    It should be Ok to use a 3.4K for the divider. It is recommended to select 3.48K value based on the availability.

    16. Do the differential signal pins (USB, etc.) have the capabilities to adjust the swing of the voltage?

    No.

    Note: 

    Ensure the recommended capacitors are provided for the VBUS supply near to the connector (Host > 120 uF and Device (1-10 uF))

    USB0_DRVVBUS has an internal pulldown enabled by default.

    Refer below documents during the USB interface design.

    Recommended References for review and design of custom board
    AM64x
    Data sheet
    AM64x Sitara Processors datasheet
    www.ti.com/.../sprsp56
    Hardware Design Guide
    www.ti.com/.../sprad67
    Schematic Design and Review Checklist for AM64x
    www.ti.com/.../spracu5
    DDR Board Design and Layout Guidelines
    www.ti.com/.../spracu1
    DDR Board Design and Layout Guidelines
    www.ti.com/.../sprad06
    Errata
    https://www.ti.com/lit/pdf/sprz457

    AM243x

    Data sheet
    AM243x SitaraTm Microcontrollers datasheet 
    www.ti.com/.../sprsp65


    Hardware Design Guide
    www.ti.com/.../sprad67
    Schematic Design and Review Checklist for AM64x
    www.ti.com/.../spracu5
    DDR Board Design and Layout Guidelines
    www.ti.com/.../spracu1
    DDR Board Design and Layout Guidelines (AM62x)
    www.ti.com/.../sprad06
    Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0
    www.ti.com/.../sprz457

    EVM for ALV package
    TMDS243EVM AM243x evaluation module for Arm® Cortex®-R5F-based MCUs
    www.ti.com/.../TMDS243EVM
    Design files


    www.ti.com/.../sprr465
    TMDS243DC01EVM
    AM243x and AM64x evaluation module breakout board for high-speed expansion
    www.ti.com/.../TMDS243DC01EVM
    www.ti.com/.../sprr443

    TMDS64DC01EVM AM64x IO-link and high-speed breakout card
    www.ti.com/.../TMDS64DC01EVM
    dr-download.ti.com/.../sprr457.zip

    Launchpad for ALX package
    LP-AM243 AM243x general purpose LaunchPadTm development kit for Arm®-based MCU
    www.ti.com/.../LP-AM243
    www.ti.com/.../sprr433

    BP-AM2BLDCSERVO
    AM2x Brushless-DC (BLDC) Servo Motor BoosterPack
    www.ti.com/.../BP-AM2BLDCSERVO
    www.ti.com/.../sbar023

    BOOSTXL-IOLINKM-8 Eight port IO-Link master BoosterPack
    www.ti.com/.../BOOSTXL-IOLINKM-8

    Regards,

    Lavanya M R.

  • Hi Board designers, 

    Additional inputs regarding USB RCALIB resistor implementation:

    The IP specification TI received from the USB PHY design team defined a 500 ohm +/-1% calibration resistor. A few weeks ago another customer reminded us 500 ohms is not a standard value for 1% resistors. They were having problems sourcing a 500 ohm +/-1%, so asked if the could use a 499 ohm +/-1% resistor.

    I ask the USB PHY team if we could change the recommendation from 500 ohm +/-1% to 499 ohm +/-1% to make resistor selection easier for our customers. They confirmed this would be okay, so we changed the recommendation in the datasheet.

    I assume your board has two 1 kohm +/-1% resistors connected in parallel, and you are asking if this will be okay. This should be okay since the USB PHY was initially designed for a 500 ohm +/-1% resistor.

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Refer below section of the TRM for information related to USB2 polarity revu

    • USB2 PHY:
    – Fully compliant with UTMI+ Level 3 specification revision 1.0
    – Supports high-speed (480 Mbps), full-speed (12 Mbps) and low-speed (1.5 Mbps) data rates
    – Supports battery charging BC1.2v specification
    – Supports host, peripherals and OTG 2.0 (dual role device) applications
    – Supports D+/D- lane reversal for flexible board integration
    – Supports USB low-power states; namely, suspend and link power management (LPM)
    – Supports internal comparators for monitoring OTG voltage thresholds
    – Supports multiple PLL reference clocks
    – Supports internal PLL for high-speed (480 MHz) clock and data recovery (CDR) operation
    – Integrated termination resistors (45 Ω, 1.5 KΩ, and 15 KΩ)
    – Supports built-in self-test (BIST) for production testing
    – 3.3-V ESD support on VBUS

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Refer below explanation for connecting the USB interface signals directly:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/261717/am335x-series-resistors-on-usb_dp-usb_dm/914980?tisearch=e2e-sitesearch&keymatch=userdisplayname%25253A%252522Peaves%252522%252520%252526%252526%252520reflection#914980

    According to the schematic checklist (processors.wiki.ti.com/.../AM335x_Schematic_Checklist of AM335x,

    "USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points."

    Can I know the reason why?


    (observed problem)

    * when connected 10 ohm series resistors (for avoiding ESD problem), error happened (at the driver) while transferring data through USB port

    * when replacing it with 0 ohm, the error does not happen

    * when comparing Eye-Patterns, there is no big difference (both meet the specification)


    The additional 10 ohms of resistance creates an impedance mismatch in the transmission line.

    This impedance mismatch causes a portion of the energy in the waveform propagating down the transmission line to be reflected. The reflection will be combined with data patterns propagating down the transmission line with the result being certain data patterns distorted beyond recognition. Some data patterns may be affected more than others due to many variables related to these reflections. It is possible the standard test packet may not be significantly affected by this impedance mismatch.

    It is very important to maintain a 90 ohm differential transmission line to prevent any reflections.

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Inputs related to USBx_VBUS voltage 

    My customer wants to know (1) the USB0_VBUS input pin detect HI_min and LOW_max thresholds, as well as (2) how over-voltage clamping occurs on that pin;
    It is said that the buffer is powered by three domains (0.85V/1.8V/3.3V) and probably only one is attached to the 'substrate clamp diode'?
    Also (3), what would the allowed max clamp current be, non-destructive, via the substrate, either with or without power to the CPU?

    We do not define VBUS thresholds. VBUS thresholds are defined in the USB specification. The thresholds were designed to be compliant to the USB specifications and validated via USB-IF compliance tests. 

    The VBUS input has an ESD clamp to the 3.3V rail. The USB VBUS Design Guidelines section of the AM64x datasheet defines the VBUS connection topology. This voltage divider / clamp circuit allows VBUS to go up to 30V without harming the VBUS input. The Zener diode could be removed and a 20 kohm resistor could be substituted for the 16.5 kohm and 3.3.48 kohm resistors if your system will never apply a VBUS potential greater than 5.5V.

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Inputs related to use of Common Mode Choke

    Page 11

    USB3.0 USB2 common mode filter ACM2012-900-2P-T002

    Common-mode chokes may be needed for EMI/EMC control. Note that these may reduce the signal amplitude and degrade performance.

    https://www.ti.com.cn/cn/lit/an/sprack7b/sprack7b.pdf

    https://www.ti.com/lit/an/sprabt8a/sprabt8a.pdf

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Input related to USBx_RCALIB calib resistor

    The USB port will have undefined behavior if it doesn’t have the proper calibration resistor connected. The USB port will have undefined behavior if it doesn’t have the proper calibration resistor connected.
    Operating without the proper calibration resistor is not a valid use case. 

    The calibration resistor is a reference standard that is used by the PHY calibration circuits to adjust voltage thresholds, IO impedances, and internal bias points of the analog circuits implemented in the PHY.

     Regards,

    Sreenivasa 

  • Hi Board designers, 

    Inputs related to USB interface.

    I would like to use the USB function only for as a device, not host,  please tell me the following two points.
    ・Is it correct that CC1 and CC2 pins that come in from the outside are pulled down with 5.1kΩ?
    ・Is it correct that set the AM64x pin (U16, USB0_ID) as not connect?

    AM64x does not have USB CC pins. It requires a companion device to implement USB Type-C.

    Connecting 5.1K ohm resistors from each USB Type-C CC pin to ground defines an Up-stream Facing Port (UFP), which defaults to device mode. You need to select a USB Type-C companion device and connect it as described in the respective device datasheet.

    The AM64x USB0_ID should be open-circuit when you are wanting the AM64x USB port to operate in device mode, or connected to ground when you are wanting the AM64x USB port to operate in host mode,  Note: You should never connect the USB0_ID pin to a circuit capable of sourcing current.  The USB0_ID pin should only be connected to a circuit that sinks current.

    A UFP is expected to monitor the voltage of the CC pins to determine current sourcing capabilities of the DFP. The detection thresholds are 0.2V, 0.66V, and 1.23V. The DFP is capable of sourcing 500mA if USB 2.0 or 900mA if USB 3.0 when the UFP detects a voltage between 0.2V and 0.66V. The DFP is capable of sourcing 1.5A when the UFP detects a voltage between 0.66V and 1.23V. The DFP is capable of sourcing 3.0A when the UFP detects a voltage greater than 1.23V.

    For this use case, you should be able to use the USB0_DRVVBUS pin as GPIO1-79 if you need another GPIO. However, this pin has an internal pull-down that is turned on by defaults, so you may need to account for it if you use the pin as a GPIO.

    Monitoring the voltage of the CC pins may not be required if you are not using VBUS to power any circuits in your system. I recommend you confirm this is the case by reading the USB Type-C specification.

    VBUS is not used to power the circuits in the system.
    In this application, it is used only as a device, so I understand that the CCpin should be a 5.1k pull-down.
    Please let me know if there is any discrepancy in my understanding.

    I think you are okay with these connections.

    I have some questions about connections between AM64 and TUSB320LA.

    Q1: What is absolute maximum voltage on USB0_ID pin?

    I'm going to skip this question for now because I do not think it is relevant.


    Q2: What is the first power source of USB0_ID pin from outside? Three source are written in datasheet.

    I'm going to skip this question for now because I do not think it is relevant.


    Q3: What is the threshold voltage for Low detection on USB0_ID pin? 

    You should never apply any potential to this pin. This pin should only be connected to a resistor that is connected to VSS. There is a an internal circuit that measures the resistance of this pin to VSS. Different resistor values are used to indicate the USB mode of operation and the resistors values are defined in the USB specification.


    Q4: Is it able to connect the ID output of TUSB320LA to AM64 USB0_ID pin?

    Only if the TUSB320LA output looks like a resistor connected to VSS and does not source any potential to the pin.


    Q5: Is it able to pull the USB0_ID pin Low by TUSB320LA?

    Only if the TUSB320LA output looks like a resistor connected to VSS and does not source any potential to the pin.


    Q6: Now we connect the PU resister in USB0_ID line. Is it okey?

    What is the threshold resistance to detect High or Low on ID pin?

    It seems that the open drain resistance of TUSB320 ID pin is 250 ohm, according to the datasheet (Max. Low-level output voltage of open drain is 0.4 V at -1.6 mA). Mr. Nagata taught me that.

    I have inserted a snapshot of valid ID resistor values as defined by USB-IF.

    I do not think you will have a problem with the impedance of the TUSB320 ID pin being able to indicate host function (RID_GND).  However, you need to be careful with one of the recommendations mentioned in the TUSB320 datasheet.

    The datasheet recommends the ID pin be connected to an external 200k ohm pull-up that is connected to the TUSB320 VDD 5V supply. This is a very bad recommendation without additional warnings related to potential EOS concerns when connected to devices like AM64x that cannot tolerate external sources, especially 5V sources. It is very likely the recommended circuit topology would destroy AM64x.

    The TUSB320 ID pin is not fail-safe and they do not want you to apply any potential to it when the device is not powered. The AM64x ID pin has an internal current source that will be turned on when software initiates a ID resistance measurement. The ID resistance measurement should never be performed while the TUSB320 device is not powered to prevent the AM64x device from sourcing current into the TUSB320 ID pin which is not fail-safe. This is something you need to understand and implement appropriate system level precautions that prevent this from occurring.

    I was not able to find the table of snapshot in datasheet version 3. Are you going to include the documents in the next datasheet version?

    We only reference the respective USB and PCIe specifications in the datasheet for these industry standard interfaces since AM64x is compliant to the standards.

    • Does the USB controller  for AM64x have ID pin?

    Yes, AM64x has a pin named USB0_ID. See the AM64x datasheet.

    (+) USB host and Peripheral modes operation - Processors forum - Processors - TI E2E support forums

    Regards,

    Sreenivasa

  • Hi Board Designers,

    Inputs related to VBUS connection

    regards,

    Sreenivasa

  • Hi Board Designers,

    Refer below inputs related to USB compliance and Adjustment:

    (+) AM625: USB2.0 compliance test mode - Processors forum - Processors - TI E2E support forums

    My customer wants to put USB into compliance test mode.
    USB2.0, High-Speed mode, Type-C connector, Host and Device.

    They are asking how to configure USB.
    BTW, o they need register level configuration.But here is some guidelines:

    - for AM625 USB in host mode, it is xHCI compliant controller, please refer to the xHCI Specification for entering test mode.

    - for AM625 USB in device mode, please refer to the DWC3 driver in Linux kernel, file drivers/usb/dwc3/gadget.c, mainly in function dwc3_gadget_set_test_mode().

    (+) AM625: USB2.0 compliance test mode with Linux SDK - Processors forum - Processors - TI E2E support forums

    This is additional questions to the original post.
    The customer wants to put USB2.0 into compliance test mode under Linux SDK.
    USB2.0, High-Speed mode, Type-C connector, Host and Device.

    Could you let me know the test procedure or document?

    The USB2.0 compliance test procedure is documented by USB-IF.

    (+) AM62P-Q1: Adjust USB 2.0 high speed PHY parameters - Processors forum - Processors - TI E2E support forums

    AM62P-Q1: Adjust USB 2.0 high speed PHY parameters

    Could you help to provide more details on the setup you are using that is causing issues? Is this with host or device mode? Do you have common mode chokes and/or ESD diodes on D+/D- lines? We have seen having these might deteriorate signal quality. Are you using the USB-IF electrical analysis tool for test packet waveform analysis? I suppose you are using near end in order to use worst-case eye mask. What vCore configuration (0.75V or 0.85V) are you using? The USB2.0 IP itself does support HS differential voltage swing tuning, but this has not been validated within TI and thus it is not currently supported. Can you provide more details on the failure being observed? Is it marginal?

    https://www.usb.org/document-library/usb-20-electrical-compliance-test-specification-version-107

    (+) AM625-Q1: Regarding PCB Pattern, should customer consider the pin delay in SoC for eMMC / QSPI / USB for pattern layout of PCB? - Processors forum - Processors - TI E2E support forums

    For the propagation delay, the delay here is only for the peripheral traces on the board. There is no need to include any package level propagation delay.

    (+) AM625-Q1: Termination on USB lines - Processors forum - Processors - TI E2E support forums

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/261717/am335x-series-resistors-on-usb_dp-usb_dm/914980

    According to the schematic checklist (processors.wiki.ti.com/.../AM335x_Schematic_Checklist of AM335x,

    "USBx_DP and USB_DM should never have any series resistors or capacitance on these signals. These signals should be straight traces to the connector with no stubs or test points."

    Can I know the reason why?


    (observed problem)

    * when connected 10 ohm series resistors (for avoiding ESD problem), error happened (at the driver) while transferring data through USB port

    * when replacing it with 0 ohm, the error does not happen

    * when comparing Eye-Patterns, there is no big difference (both meet the specification)


    The additional 10 ohms of resistance creates an impedance mismatch in the transmission line.

    This impedance mismatch causes a portion of the energy in the waveform propagating down the transmission line to be reflected. The reflection will be combined with data patterns propagating down the transmission line with the result being certain data patterns distorted beyond recognition. Some data patterns may be affected more than others due to many variables related to these reflections. It is possible the standard test packet may not be significantly affected by this impedance mismatch.

    It is very important to maintain a 90 ohm differential transmission line to prevent any reflections.

    USB guidelines

    Follow the below guidelines.

    https://www.ti.com/lit/an/spraar7j/spraar7j.pdf

    Regards,

    Sreenivasa

  • Hi Board designers, 

    Refer additional inputs 

    (+) TUSB321: Query on USBC_ID pull-up value - Interface forum - Interface - TI E2E support forums

    TUSB321: Query on USBC_ID pull-up value

    Please support the below query:

    According to the TI's TUSB231 chip datasheet - the recommended external pull-up resistor attached to the TUSB321 USBC_ID output (open drain) shall be 200K.

    In the latest AM67x TI EVM  schematic –“PROC170E3B(002)_SCH.pdf” a pull-up resistor R608 with value of 10K is used. 

    (+) AM67: TUSB321 id pin resistor value in AM67 reference design - Processors forum - Processors - TI E2E support forums

    The question came from this E2E query:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1554882/am67-tusb321-id-pin-resistor-value-in-am67-reference-design

     

    Do you have a recommendation on the pullup value.

    Is there a concern if 10K is used on the EVM ?

    The ID pin on the TUSB321 acts as an open-drain pin, so an external pull-up resistor is needed to allow the pin to pull high. A value of 200Kohm helps ensure that when the ID pin is pulled-down by the TUSB321, the weak pull-up from the 200Kohm resistor won't stop the voltage on the pin from going down to 0V. 10Kohm can be used, but it would need to be tested to ensure that when the ID pin is pulled-low by the TUSB321, the voltage of the pin goes low enough to signal the power switch to enable VBUS.

    Thank you for the inputs, appreciated. 

    The AM67x EVM has been implemented with 10K and seems to be working. 

    If i  understand correctly the recommendation is to use 200K but you do not see any concerns in case a 10K is used and functionally working.

    Please let me know your thoughts.

    Correct, while it's the recommendation, if you aren't seeing any functional issues then I don't see any issues.

    Regards,

    Sreenivasa