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[FAQ] AM64X/ AM62X : How to Reset the SOC when WDT timer expires in AM64X and AM62X?

Swargam Anil
Mastermind 34620 points
Part Number: AM6442

Introduction:

The primary application of a watchdog timer is as a system monitor to detect and reset an "out of control" SOC.

When program execution goes wrong or software or devices are not functioning properly, the watchdog timer will help keep the SOC in a known state.

  • +1
    TI__Mastermind 34620 points

    Current AM64X and AM62X devices support DWWD (Digital Windowed Watch Dog). 

    The DWWD opens a configurable time window in which the watchdog must be serviced. Any attempt to service the watchdog outside this time window, or a failure to service the watchdog in this time window, will cause the watchdog to generate an NMI for the self-CPU.

    In this situation, who should reset the crashed core? Typically, the expectation is to self-reset the SOC when WDT has expired, but this is currently not supported by MCU+ SDK code running on AM64X and AM62X devices. (Note, Linux will reset the processor after a Linux watchdog timer generates an NMI)

  • +1 in reply to Swargam Anil
    TI__Mastermind 34620 points


    Solution :

    Configure ESM to route the RTI interrupts to error output, which is one of the warm reset sources.

    RTI Time Out  - > ESM Event  - >  CTRL MMR Register (control reset is activated from the ESM error event or not from MMR Registers ).

    Typically, you have to follow the steps below.

     1. Set the Watch dog expiration time.

    2. Initialize ESM module

    3. Route WDT expired event to ESM output and interrupt priority should be configured as High 

    4. Control the CTRL_MMR Register to determine whether the SOC should get reset through the ESM module or not

  • +1 in reply to Swargam Anil
    TI__Genius 13406 points


    Example :

    1. You can use the SDL RTI module APIs for configuring the WDG timer. It is available in the MCU+SDK of AM64x and AM62x. 

    We can select the RTI instance based on the core we are running the Wdg timer and the SoC. 

    2. You can configure the RTI events in the ESM configuration by looking at the Table 10-2 and Table 10-3 of AM62x TRM and Table 9-68 and Table 9-71 of AM64x TRM. 

    ESM Configuration and Initialization 

    In the above screenshot, Main ESM event 163 is configured and a high priority interrupt is set for it as event 163 corresponds to Wkup_RTI0 in AM62x. The configuration in AM64x would also be similar. 

    For understanding the bitmap structure and ESM configuration, you can look at FAQ attached here .

    3. Set the 17th bit of WKUP_CTRL_MMR0 register in AM62x or CTRL_MMR0 register in AM64x to 0 in order to enable the reset of SoC by the ESM module.

  • +1 in reply to Nihar Potturu
    TI__Genius 13406 points

    Conclusion :

    After making the above changes, you can see the SoC getting reset once the Wdg timer expires.

    Attaching the AM62x and AM64X example applications below :

    8345.Wdg_Reset_AM62x.zip

    2068.WDG_Reset_AM64X.zip

  • +1 in reply to Nihar Potturu
    TI__Mastermind 34620 points

    NOTE :

    1. Individual reset cores are not supported for watch dog expiration on AM62X and AM64X devices.
    2. The ESM error output should be configured as high (if you configure priority as low, SOC will not get reset).
    3. If you enabled high-priority interrupts for other ESM errors, there could be a chance to reset SOC due to ECC errors as well. In this case, priority should be configured as high for RTI errors, and for other ESM errors, priority should be configured as low.