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[FAQ] TDA4VH-Q1: DDR_SHARED_MEM alignment requirement for RAT configuration

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VM, TCA9539

My SDK version:
        linux:  ti-processor-sdk-linux-adas-j784s4-evm-09_01_00_06 

        rtos:  ti-processor-sdk-rtos-j784s4-evm-09_01_00_06


I tried to change the heap memory size of MCU2_0, after referring to the instruction manual, I changed the "
Rtos_sdk vision_apps/platform/j784s4 / rtos/gen_linker_mem_map.py " files, and execute the script, obtained the corresponding generated file. The changes are as follows:
        
Copy the contents of the k3-j784s4-rtos-memory-map.dtsi file to the appropriate path of the Linux SDK and compile and install it according to the instructions in the instruction manual.

    1. To generate the memory map related files do below

        cd vision_apps/platform/<soc>/rtos
        python3 gen_linker_mem_map.py

    2. Copy the contents of the generated k3-{SOC}-rtos-memory-map.dtsi file and replace the reserved_memory section of the k3-{SOC}-rtos-memory-map.dtsi file that is located here:

              PSDK_LINUX_PATH/board-support/linux*/arch/arm64/boot/dts/ti

    3.1  Rebuild the dtb and dtbo from the PSDK_LINUX_PATH directory with the following:

                 make linux-dtbs

    3.2  Install the dtb and dtbo to the rootfs/boot folder on the SD card from the same directory with the following

                sudo make linux-dtbs_install; sync

After compiling and installing both the RTOS and Linux into the SD card, boot the system:

        

        From the memory size and memory address, you can see that I have configured it successfully.

Running my test program produces the following error:

        
        
What is the cause of this problem? How to fix it?
Above, thank you

  • Hi,

    Could you please share me the system_memory_map.html file that is generated from the python script?

    It looks like you might have crossed the 2GB DDR space and entered 64bit address space for R5.

    Regards,

    Nikhil

  • <!DOCTYPE html>
    <html>
    <style type="text/css">
    .tg {border-collapse:collapse;border-spacing:0;border-color:#999;}
    .tg td{font-family:Arial, sans-serif;font-size:14px;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#444;background-color:#F7FDFA;}
    .tg th{font-family:Arial, sans-serif;font-size:14px;font-weight:normal;padding:10px 5px;border-style:solid;border-width:1px;overflow:hidden;word-break:normal;border-color:#999;color:#fff;background-color:#26ADE4;}
    .tg .tg-kftd{background-color:#efefef;text-align:left;vertical-align:top}
    .tg .tg-6sgx{background-color:#ffffff;text-align:left;vertical-align:top}
    .tg .tg-fjir{background-color:#343434;color:#ffffff;text-align:left;vertical-align:top}
    </style>

    <head>
    <title>System Memory Map for Linux+RTOS mode</title>
    </head>
    <body>
    <h1>System Memory Map for Linux+RTOS mode</h1>
    <p>Note, this file is auto generated using PyTI_PSDK_RTOS tool</p>
    <table class="tg">
    <tr>
    <th class="tg-fjir">Name</th>
    <th class="tg-fjir">Start Addr</th>
    <th class="tg-fjir">End Addr</th>
    <th class="tg-fjir">Size </th>
    <th class="tg-fjir">Attributes</th>
    <th class="tg-fjir">Description</th>
    </tr>
    <tr>
    <td class="tg-kftd">MAIN_OCRAM_MCU2_0</td>
    <td class="tg-kftd">0x60000000</td>
    <td class="tg-kftd">0x6003FFFF</td>
    <td class="tg-kftd">256.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Main OCRAM for MCU2_0</td>
    </tr>
    <tr>
    <td class="tg-6sgx">MAIN_OCRAM_MCU2_1</td>
    <td class="tg-6sgx">0x60040000</td>
    <td class="tg-6sgx">0x6007FFFF</td>
    <td class="tg-6sgx">256.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Main OCRAM for MCU2_1</td>
    </tr>
    <tr>
    <td class="tg-kftd">MAIN_OCRAM_MCU4_0</td>
    <td class="tg-kftd">0x60080000</td>
    <td class="tg-kftd">0x600FFFFF</td>
    <td class="tg-kftd">512.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Main OCRAM for MCU4_0</td>
    </tr>
    <tr>
    <td class="tg-6sgx">L2RAM_C7x_1</td>
    <td class="tg-6sgx">0x64800000</td>
    <td class="tg-6sgx">0x6486FFFF</td>
    <td class="tg-6sgx">448.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">L2 for C7x_1</td>
    </tr>
    <tr>
    <td class="tg-kftd">L1RAM_C7x_1</td>
    <td class="tg-kftd">0x64E00000</td>
    <td class="tg-kftd">0x64E03FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">L1 for C7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">L2RAM_C7x_2</td>
    <td class="tg-6sgx">0x65800000</td>
    <td class="tg-6sgx">0x6586FFFF</td>
    <td class="tg-6sgx">448.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">L2 for C7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">L1RAM_C7x_2</td>
    <td class="tg-kftd">0x65E00000</td>
    <td class="tg-kftd">0x65E03FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">L1 for C7x_2</td>
    </tr>
    <tr>
    <td class="tg-6sgx">L2RAM_C7x_3</td>
    <td class="tg-6sgx">0x66800000</td>
    <td class="tg-6sgx">0x6686FFFF</td>
    <td class="tg-6sgx">448.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">L2 for C7x_3</td>
    </tr>
    <tr>
    <td class="tg-kftd">L1RAM_C7x_3</td>
    <td class="tg-kftd">0x66E00000</td>
    <td class="tg-kftd">0x66E03FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">L1 for C7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">L2RAM_C7x_4</td>
    <td class="tg-6sgx">0x67800000</td>
    <td class="tg-6sgx">0x6786FFFF</td>
    <td class="tg-6sgx">448.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">L2 for C7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">L1RAM_C7x_4</td>
    <td class="tg-kftd">0x67E00000</td>
    <td class="tg-kftd">0x67E03FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">L1 for C7x_4</td>
    </tr>
    <tr>
    <td class="tg-6sgx">MSMC_C7x_1</td>
    <td class="tg-6sgx">0x68000000</td>
    <td class="tg-6sgx">0x682FFFFF</td>
    <td class="tg-6sgx"> 3.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">MSMC for C7x_1</td>
    </tr>
    <tr>
    <td class="tg-kftd">MSMC_C7x_2</td>
    <td class="tg-kftd">0x69000000</td>
    <td class="tg-kftd">0x692FFFFF</td>
    <td class="tg-kftd"> 3.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">MSMC for C7x_2</td>
    </tr>
    <tr>
    <td class="tg-6sgx">MSMC_C7x_3</td>
    <td class="tg-6sgx">0x6A000000</td>
    <td class="tg-6sgx">0x6A2FFFFF</td>
    <td class="tg-6sgx"> 3.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">MSMC for C7x_3</td>
    </tr>
    <tr>
    <td class="tg-kftd">MSMC_C7x_4</td>
    <td class="tg-kftd">0x6B000000</td>
    <td class="tg-kftd">0x6B2FFFFF</td>
    <td class="tg-kftd"> 3.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">MSMC for C7x_4</td>
    </tr>
    <tr>
    <td class="tg-6sgx">MSMC_MPU1</td>
    <td class="tg-6sgx">0x70000000</td>
    <td class="tg-6sgx">0x7001FFFF</td>
    <td class="tg-6sgx">128.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">MSMC reserved for MPU1 for ATF</td>
    </tr>
    <tr>
    <td class="tg-kftd">MSMC_DMSC</td>
    <td class="tg-kftd">0x707F0000</td>
    <td class="tg-kftd">0x707FFFFF</td>
    <td class="tg-kftd">64.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">MSMC reserved for DMSC IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU1_0_IPC</td>
    <td class="tg-6sgx">0xA0000000</td>
    <td class="tg-6sgx">0xA00FFFFF</td>
    <td class="tg-6sgx">1024.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU1_0 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU1_0_RESOURCE_TABLE</td>
    <td class="tg-kftd">0xA0100000</td>
    <td class="tg-kftd">0xA01003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU1_0 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU1_0</td>
    <td class="tg-6sgx">0xA0100400</td>
    <td class="tg-6sgx">0xA0FFFFFF</td>
    <td class="tg-6sgx">15.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU1_0 for code/data</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU1_1_IPC</td>
    <td class="tg-kftd">0xA1000000</td>
    <td class="tg-kftd">0xA10FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU1_1 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU1_1_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xA1100000</td>
    <td class="tg-6sgx">0xA11003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU1_1 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU1_1</td>
    <td class="tg-kftd">0xA1100400</td>
    <td class="tg-kftd">0xA1FFFFFF</td>
    <td class="tg-kftd">15.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU1_1 for code/data</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU2_0_IPC</td>
    <td class="tg-6sgx">0xA2000000</td>
    <td class="tg-6sgx">0xA20FFFFF</td>
    <td class="tg-6sgx">1024.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU2_0 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU2_0_RESOURCE_TABLE</td>
    <td class="tg-kftd">0xA2100000</td>
    <td class="tg-kftd">0xA21003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU2_0 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU2_0</td>
    <td class="tg-6sgx">0xA2100400</td>
    <td class="tg-6sgx">0xA3FFFFFF</td>
    <td class="tg-6sgx">31.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU2_0 for code/data</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU2_1_IPC</td>
    <td class="tg-kftd">0xA4000000</td>
    <td class="tg-kftd">0xA40FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU2_1 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU2_1_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xA4100000</td>
    <td class="tg-6sgx">0xA41003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU2_1 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU2_1</td>
    <td class="tg-kftd">0xA4100400</td>
    <td class="tg-kftd">0xA4FFFFFF</td>
    <td class="tg-kftd">15.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU2_1 for code/data</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU3_0_IPC</td>
    <td class="tg-6sgx">0xA5000000</td>
    <td class="tg-6sgx">0xA50FFFFF</td>
    <td class="tg-6sgx">1024.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU3_0 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU3_0_RESOURCE_TABLE</td>
    <td class="tg-kftd">0xA5100000</td>
    <td class="tg-kftd">0xA51003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU3_0 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU3_0</td>
    <td class="tg-6sgx">0xA5100400</td>
    <td class="tg-6sgx">0xA5FFFFFF</td>
    <td class="tg-6sgx">15.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU3_0 for code/data</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU3_1_IPC</td>
    <td class="tg-kftd">0xA6000000</td>
    <td class="tg-kftd">0xA60FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU3_1 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU3_1_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xA6100000</td>
    <td class="tg-6sgx">0xA61003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU3_1 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU3_1</td>
    <td class="tg-kftd">0xA6100400</td>
    <td class="tg-kftd">0xA6FFFFFF</td>
    <td class="tg-kftd">15.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU3_1 for code/data</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU4_0_IPC</td>
    <td class="tg-6sgx">0xA7000000</td>
    <td class="tg-6sgx">0xA70FFFFF</td>
    <td class="tg-6sgx">1024.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU4_0 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU4_0_RESOURCE_TABLE</td>
    <td class="tg-kftd">0xA7100000</td>
    <td class="tg-kftd">0xA71003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU4_0 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU4_0</td>
    <td class="tg-6sgx">0xA7100400</td>
    <td class="tg-6sgx">0xA7FFFFFF</td>
    <td class="tg-6sgx">15.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU4_0 for code/data</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU4_1_IPC</td>
    <td class="tg-kftd">0xA8000000</td>
    <td class="tg-kftd">0xA80FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU4_1 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU4_1_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xA8100000</td>
    <td class="tg-6sgx">0xA81003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU4_1 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU4_1</td>
    <td class="tg-kftd">0xA8100400</td>
    <td class="tg-kftd">0xA8FFFFFF</td>
    <td class="tg-kftd">15.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU4_1 for code/data</td>
    </tr>
    <tr>
    <td class="tg-6sgx">IPC_VRING_MEM</td>
    <td class="tg-6sgx">0xAC000000</td>
    <td class="tg-6sgx">0xAEFFFFFF</td>
    <td class="tg-6sgx">48.00 MB</td>
    <td class="tg-6sgx"></td>
    <td class="tg-6sgx">Memory for IPC Vring's. MUST be non-cached or cache-coherent</td>
    </tr>
    <tr>
    <td class="tg-kftd">APP_LOG_MEM</td>
    <td class="tg-kftd">0xAF000000</td>
    <td class="tg-kftd">0xAF03FFFF</td>
    <td class="tg-kftd">256.00 KB</td>
    <td class="tg-kftd"></td>
    <td class="tg-kftd">Memory for remote core logging</td>
    </tr>
    <tr>
    <td class="tg-6sgx">TIOVX_OBJ_DESC_MEM</td>
    <td class="tg-6sgx">0xAF040000</td>
    <td class="tg-6sgx">0xB0FFFFFF</td>
    <td class="tg-6sgx">31.75 MB</td>
    <td class="tg-6sgx"></td>
    <td class="tg-6sgx">Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent</td>
    </tr>
    <tr>
    <td class="tg-kftd">APP_FILEIO_MEM</td>
    <td class="tg-kftd">0xB1000000</td>
    <td class="tg-kftd">0xB13FFFFF</td>
    <td class="tg-kftd"> 4.00 MB</td>
    <td class="tg-kftd"></td>
    <td class="tg-kftd">Memory for remote core file operations</td>
    </tr>
    <tr>
    <td class="tg-6sgx">TIOVX_LOG_RT_MEM</td>
    <td class="tg-6sgx">0xB1400000</td>
    <td class="tg-6sgx">0xB1FFFFFF</td>
    <td class="tg-6sgx">12.00 MB</td>
    <td class="tg-6sgx"></td>
    <td class="tg-6sgx">Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_1_IPC</td>
    <td class="tg-kftd">0xB2000000</td>
    <td class="tg-kftd">0xB20FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_1 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_1_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xB2100000</td>
    <td class="tg-6sgx">0xB21003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_1 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_1_BOOT</td>
    <td class="tg-kftd">0xB2200000</td>
    <td class="tg-kftd">0xB22003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_1 for boot section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_1_VECS</td>
    <td class="tg-6sgx">0xB2400000</td>
    <td class="tg-6sgx">0xB2403FFF</td>
    <td class="tg-6sgx">16.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_1 for vecs section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_1_SECURE_VECS</td>
    <td class="tg-kftd">0xB2600000</td>
    <td class="tg-kftd">0xB2603FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_1 for secure vecs section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_1</td>
    <td class="tg-6sgx">0xB2800000</td>
    <td class="tg-6sgx">0xB3FFFFFF</td>
    <td class="tg-6sgx">24.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address for C7x_1 code/data section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_2_IPC</td>
    <td class="tg-kftd">0xB4000000</td>
    <td class="tg-kftd">0xB40FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_2 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_2_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xB4100000</td>
    <td class="tg-6sgx">0xB41003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_2 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_2_BOOT</td>
    <td class="tg-kftd">0xB4200000</td>
    <td class="tg-kftd">0xB42003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_2 for boot section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_2_VECS</td>
    <td class="tg-6sgx">0xB4400000</td>
    <td class="tg-6sgx">0xB4403FFF</td>
    <td class="tg-6sgx">16.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_2 for vecs section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_2_SECURE_VECS</td>
    <td class="tg-kftd">0xB4600000</td>
    <td class="tg-kftd">0xB4603FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_2 for secure vecs section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_2</td>
    <td class="tg-6sgx">0xB4800000</td>
    <td class="tg-6sgx">0xB5FFFFFF</td>
    <td class="tg-6sgx">24.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address for C7x_2 code/data section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_3_IPC</td>
    <td class="tg-kftd">0xB6000000</td>
    <td class="tg-kftd">0xB60FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_3 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_3_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xB6100000</td>
    <td class="tg-6sgx">0xB61003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_3 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_3_BOOT</td>
    <td class="tg-kftd">0xB6200000</td>
    <td class="tg-kftd">0xB62003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_3 for boot section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_3_VECS</td>
    <td class="tg-6sgx">0xB6400000</td>
    <td class="tg-6sgx">0xB6403FFF</td>
    <td class="tg-6sgx">16.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_3 for vecs section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_3_SECURE_VECS</td>
    <td class="tg-kftd">0xB6600000</td>
    <td class="tg-kftd">0xB6603FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_3 for secure vecs section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_3</td>
    <td class="tg-6sgx">0xB6800000</td>
    <td class="tg-6sgx">0xB7FFFFFF</td>
    <td class="tg-6sgx">24.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address for C7x_3 code/data section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_4_IPC</td>
    <td class="tg-kftd">0xB8000000</td>
    <td class="tg-kftd">0xB80FFFFF</td>
    <td class="tg-kftd">1024.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_4 for Linux IPC</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_4_RESOURCE_TABLE</td>
    <td class="tg-6sgx">0xB8100000</td>
    <td class="tg-6sgx">0xB81003FF</td>
    <td class="tg-6sgx">1024 B</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_4 for Linux resource table</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_4_BOOT</td>
    <td class="tg-kftd">0xB8200000</td>
    <td class="tg-kftd">0xB82003FF</td>
    <td class="tg-kftd">1024 B</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_4 for boot section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_4_VECS</td>
    <td class="tg-6sgx">0xB8400000</td>
    <td class="tg-6sgx">0xB8403FFF</td>
    <td class="tg-6sgx">16.00 KB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for C7x_4 for vecs section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7x_4_SECURE_VECS</td>
    <td class="tg-kftd">0xB8600000</td>
    <td class="tg-kftd">0xB8603FFF</td>
    <td class="tg-kftd">16.00 KB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for C7x_4 for secure vecs section</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7x_4</td>
    <td class="tg-6sgx">0xB8800000</td>
    <td class="tg-6sgx">0xB9FFFFFF</td>
    <td class="tg-6sgx">24.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address for C7x_4 code/data section</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU1_0_LOCAL_HEAP</td>
    <td class="tg-kftd">0xBA000000</td>
    <td class="tg-kftd">0xBA7FFFFF</td>
    <td class="tg-kftd"> 8.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU1_0 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU1_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0xBA800000</td>
    <td class="tg-6sgx">0xBAFFFFFF</td>
    <td class="tg-6sgx"> 8.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU1_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU2_0_LOCAL_HEAP</td>
    <td class="tg-kftd">0xBB000000</td>
    <td class="tg-kftd">0xC2FFFFFF</td>
    <td class="tg-kftd">128.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU2_0 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU2_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0xC3000000</td>
    <td class="tg-6sgx">0xC3FFFFFF</td>
    <td class="tg-6sgx">16.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU2_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU3_0_LOCAL_HEAP</td>
    <td class="tg-kftd">0xC4000000</td>
    <td class="tg-kftd">0xC47FFFFF</td>
    <td class="tg-kftd"> 8.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU3_0 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU3_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0xC4800000</td>
    <td class="tg-6sgx">0xC4FFFFFF</td>
    <td class="tg-6sgx"> 8.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU3_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_MCU4_0_LOCAL_HEAP</td>
    <td class="tg-kftd">0xC5000000</td>
    <td class="tg-kftd">0xC57FFFFF</td>
    <td class="tg-kftd"> 8.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">DDR for MCU4_0 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_MCU4_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0xC5800000</td>
    <td class="tg-6sgx">0xC5FFFFFF</td>
    <td class="tg-6sgx"> 8.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">DDR for MCU4_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">INTERCORE_ETH_DESC_MEM</td>
    <td class="tg-kftd">0xC6000000</td>
    <td class="tg-kftd">0xC67FFFFF</td>
    <td class="tg-kftd"> 8.00 MB</td>
    <td class="tg-kftd"></td>
    <td class="tg-kftd">Inter-core ethernet shared desc queues. MUST be non-cached or cache-coherent</td>
    </tr>
    <tr>
    <td class="tg-6sgx">INTERCORE_ETH_DATA_MEM</td>
    <td class="tg-6sgx">0xC6800000</td>
    <td class="tg-6sgx">0xC7FFFFFF</td>
    <td class="tg-6sgx">24.00 MB</td>
    <td class="tg-6sgx"></td>
    <td class="tg-6sgx">Inter-core ethernet shared data buffers. MUST be non-cached or cache-coherent</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_SHARED_MEM</td>
    <td class="tg-kftd">0xC8000000</td>
    <td class="tg-kftd">0xE5FFFFFF</td>
    <td class="tg-kftd">480.00 MB</td>
    <td class="tg-kftd"></td>
    <td class="tg-kftd">Memory for shared memory buffers in DDR</td>
    </tr>
    <tr>
    <td class="tg-6sgx">UBOOT_RELOC_MEM</td>
    <td class="tg-6sgx">0xFC000000</td>
    <td class="tg-6sgx">0xFDFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx"></td>
    <td class="tg-6sgx">Uboot DDR relocation memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x100000000</td>
    <td class="tg-kftd">0x101FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x100000000</td>
    <td class="tg-6sgx">0x101FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Non-cacheable DDR for c7x_2 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x100000000</td>
    <td class="tg-kftd">0x101FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of Non-cacheable DDR for c7x_3 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x100000000</td>
    <td class="tg-6sgx">0x101FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Non-cacheable DDR for c7x_4 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP</td>
    <td class="tg-kftd">0x102000000</td>
    <td class="tg-kftd">0x103FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x102000000</td>
    <td class="tg-6sgx">0x103FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Cacheable DDR for c7x_2 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_LOCAL_HEAP</td>
    <td class="tg-kftd">0x102000000</td>
    <td class="tg-kftd">0x103FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of Cacheable DDR for c7x_3 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x102000000</td>
    <td class="tg-6sgx">0x103FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Cacheable DDR for c7x_4 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x104000000</td>
    <td class="tg-kftd">0x105FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x104000000</td>
    <td class="tg-6sgx">0x105FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Non-cacheable DDR for c7x_2 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x104000000</td>
    <td class="tg-kftd">0x105FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of Non-cacheable DDR for c7x_3 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x104000000</td>
    <td class="tg-6sgx">0x105FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of Non-cacheable DDR for c7x_4 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_SCRATCH</td>
    <td class="tg-kftd">0x106000000</td>
    <td class="tg-kftd">0x107FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_1 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_SCRATCH</td>
    <td class="tg-6sgx">0x106000000</td>
    <td class="tg-6sgx">0x107FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_2 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_SCRATCH</td>
    <td class="tg-kftd">0x106000000</td>
    <td class="tg-kftd">0x107FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_3 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_SCRATCH</td>
    <td class="tg-6sgx">0x106000000</td>
    <td class="tg-6sgx">0x107FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_4 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x108000000</td>
    <td class="tg-kftd">0x109FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x108000000</td>
    <td class="tg-6sgx">0x109FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_1_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x108000000</td>
    <td class="tg-kftd">0x109FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_1_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x108000000</td>
    <td class="tg-6sgx">0x109FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_3_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x10A000000</td>
    <td class="tg-kftd">0x10BFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_3_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x10A000000</td>
    <td class="tg-6sgx">0x10BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_2_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x10A000000</td>
    <td class="tg-kftd">0x10BFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_2_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x10A000000</td>
    <td class="tg-6sgx">0x10BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_4_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x10C000000</td>
    <td class="tg-kftd">0x10DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_4_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x10C000000</td>
    <td class="tg-6sgx">0x10DFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_4_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-kftd">0x10C000000</td>
    <td class="tg-kftd">0x10DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_3_LOCAL_HEAP_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x10C000000</td>
    <td class="tg-6sgx">0x10DFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_2_LOCAL_HEAP</td>
    <td class="tg-kftd">0x10E000000</td>
    <td class="tg-kftd">0x10FFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x10E000000</td>
    <td class="tg-6sgx">0x10FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_1_LOCAL_HEAP</td>
    <td class="tg-kftd">0x10E000000</td>
    <td class="tg-kftd">0x10FFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_1_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x10E000000</td>
    <td class="tg-6sgx">0x10FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_3_LOCAL_HEAP</td>
    <td class="tg-kftd">0x110000000</td>
    <td class="tg-kftd">0x111FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_3_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x110000000</td>
    <td class="tg-6sgx">0x111FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_2_LOCAL_HEAP</td>
    <td class="tg-kftd">0x110000000</td>
    <td class="tg-kftd">0x111FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_2_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x110000000</td>
    <td class="tg-6sgx">0x111FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_4_LOCAL_HEAP</td>
    <td class="tg-kftd">0x112000000</td>
    <td class="tg-kftd">0x113FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_4_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x112000000</td>
    <td class="tg-6sgx">0x113FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_4_LOCAL_HEAP</td>
    <td class="tg-kftd">0x112000000</td>
    <td class="tg-kftd">0x113FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_3_LOCAL_HEAP</td>
    <td class="tg-6sgx">0x112000000</td>
    <td class="tg-6sgx">0x113FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_2_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x114000000</td>
    <td class="tg-kftd">0x115FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_1_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x114000000</td>
    <td class="tg-6sgx">0x115FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_1_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x114000000</td>
    <td class="tg-kftd">0x115FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_1_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x114000000</td>
    <td class="tg-6sgx">0x115FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_3_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x116000000</td>
    <td class="tg-kftd">0x117FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_3_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x116000000</td>
    <td class="tg-6sgx">0x117FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_2_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x116000000</td>
    <td class="tg-kftd">0x117FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_2_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x116000000</td>
    <td class="tg-6sgx">0x117FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_4_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x118000000</td>
    <td class="tg-kftd">0x119FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_4_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x118000000</td>
    <td class="tg-6sgx">0x119FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_4_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-kftd">0x118000000</td>
    <td class="tg-kftd">0x119FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_3_SCRATCH_NON_CACHEABLE</td>
    <td class="tg-6sgx">0x118000000</td>
    <td class="tg-6sgx">0x119FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_2_SCRATCH</td>
    <td class="tg-kftd">0x11A000000</td>
    <td class="tg-kftd">0x11BFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_1_SCRATCH</td>
    <td class="tg-6sgx">0x11A000000</td>
    <td class="tg-6sgx">0x11BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_1_SCRATCH</td>
    <td class="tg-kftd">0x11A000000</td>
    <td class="tg-kftd">0x11BFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_1_SCRATCH</td>
    <td class="tg-6sgx">0x11A000000</td>
    <td class="tg-6sgx">0x11BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_3_SCRATCH</td>
    <td class="tg-kftd">0x11C000000</td>
    <td class="tg-kftd">0x11DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_3_SCRATCH</td>
    <td class="tg-6sgx">0x11C000000</td>
    <td class="tg-6sgx">0x11DFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_2_SCRATCH</td>
    <td class="tg-kftd">0x11C000000</td>
    <td class="tg-kftd">0x11DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_2_SCRATCH</td>
    <td class="tg-6sgx">0x11C000000</td>
    <td class="tg-6sgx">0x11DFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_4_SCRATCH</td>
    <td class="tg-kftd">0x11E000000</td>
    <td class="tg-kftd">0x11FFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_1</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_4_SCRATCH</td>
    <td class="tg-6sgx">0x11E000000</td>
    <td class="tg-6sgx">0x11FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_2</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_4_SCRATCH</td>
    <td class="tg-kftd">0x11E000000</td>
    <td class="tg-kftd">0x11FFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_3</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_3_SCRATCH</td>
    <td class="tg-6sgx">0x11E000000</td>
    <td class="tg-6sgx">0x11FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_4</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x880000000</td>
    <td class="tg-kftd">0x881FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of non-cacheable DDR for c7x_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_1_LOCAL_HEAP_PHYS</td>
    <td class="tg-6sgx">0x882000000</td>
    <td class="tg-6sgx">0x883FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of cacheable DDR for c7x_1 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x884000000</td>
    <td class="tg-kftd">0x885FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of non-cacheable DDR for c7x_1 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_1_SCRATCH_PHYS</td>
    <td class="tg-6sgx">0x886000000</td>
    <td class="tg-6sgx">0x887FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of cacheable DDR for c7x_1 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x888000000</td>
    <td class="tg-kftd">0x889FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Non-cacheable DDR for c7x_2 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_LOCAL_HEAP_PHYS</td>
    <td class="tg-6sgx">0x88A000000</td>
    <td class="tg-6sgx">0x88BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of Cacheable DDR for c7x_2 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x88C000000</td>
    <td class="tg-kftd">0x88DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of Non-cacheable DDR for c7x_2 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_2_SCRATCH_PHYS</td>
    <td class="tg-6sgx">0x88E000000</td>
    <td class="tg-6sgx">0x88FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of cacheable DDR for c7x_2 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x890000000</td>
    <td class="tg-kftd">0x891FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of Non-cacheable DDR for c7x_3 for local heap</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_3_LOCAL_HEAP_PHYS</td>
    <td class="tg-6sgx">0x892000000</td>
    <td class="tg-6sgx">0x893FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of Cacheable DDR for c7x_3 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x894000000</td>
    <td class="tg-kftd">0x895FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of Non-cacheable DDR for c7x_3 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_3_SCRATCH_PHYS</td>
    <td class="tg-6sgx">0x896000000</td>
    <td class="tg-6sgx">0x897FFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of cacheable DDR for c7x_3 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x898000000</td>
    <td class="tg-kftd">0x899FFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of Non-cacheable DDR for c7x_4 for local heap physical addr</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_LOCAL_HEAP_PHYS</td>
    <td class="tg-6sgx">0x89A000000</td>
    <td class="tg-6sgx">0x89BFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of Cacheable DDR for c7x_4 for local heap</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS</td>
    <td class="tg-kftd">0x89C000000</td>
    <td class="tg-kftd">0x89DFFFFFF</td>
    <td class="tg-kftd">32.00 MB</td>
    <td class="tg-kftd">RWIX</td>
    <td class="tg-kftd">Physical address of Non-cacheable DDR for c7x_4 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-6sgx">DDR_C7X_4_SCRATCH_PHYS</td>
    <td class="tg-6sgx">0x89E000000</td>
    <td class="tg-6sgx">0x89FFFFFFF</td>
    <td class="tg-6sgx">32.00 MB</td>
    <td class="tg-6sgx">RWIX</td>
    <td class="tg-6sgx">Physical address of cacheable DDR for c7x_4 for Scratch Memory</td>
    </tr>
    <tr>
    <td class="tg-kftd">DDR_SHARED_MEM_PHYS</td>
    <td class="tg-kftd">0x8A0000000</td>
    <td class="tg-kftd">0x8BDFFFFFF</td>
    <td class="tg-kftd">480.00 MB</td>
    <td class="tg-kftd"></td>
    <td class="tg-kftd">Physical address of memory for shared memory buffers in DDR</td>
    </tr>
    </table>
    </body>
    </html>

  • Sorry to show it to you this way, but I didn't find a way to upload the file.

    You can copy the text content into an html file to see the corresponding content.

    According to the problem you said, how should I modify it?

    Thank you.

  • from ti_psdk_rtos_tools import *

    KB = 1024;
    MB = KB*KB;
    GB = KB*MB;

    SHARED_MEM_SIZE = 512*MB;

    #
    # Notes,
    # - recommend to keep all memory segment sizes in units of KB at least
    #

    #
    # TODO: On J721E/J7ES/TDA4VM, there are 2 DDR chipsets
    #
    # lower DDR address starts at 0x0000_8000_0000
    # higher DDR address starts at 0x0008_8000_0000
    #
    # As the address is non-contiguous it requires MMU to remap the address
    # Currently the upper 2GB is accessed by either ARM (user space)
    # C7x DSP heap/scratch space, as 32-bit cores like R5F cannot access it
    #
    # The upper DDR address is mapped contiguously from lower DDR address
    # but remapped to actual physical address using MMU
    #
    # physical lower DDR address range 0x0000_8000_0000
    # virtual lower DDR address range 0x0000_8000_0000
    #
    # physical lower DDR address range 0x0008_8000_0000
    # virtual lower DDR address range 0x0001_0000_0000
    #

    ddr_mem_addr = 0xa0000000;
    ddr_mem_size = 1*GB + 448*MB; # Last 64MB is used by Linux

    ddr_mem_addr_hi_phys = 0x880000000;
    ddr_mem_addr_hi = 0x100000000;
    ddr_mem_size_hi = 256*MB;

    msmc_mem_addr = 0x70000000;
    main_ocram_mem_addr = 0x60000000; # Note: uses RAT to translate to proper address
    main_ocram_mem_addr_phys = 0x4F02000000;

    codec_carveout_size = 2*GB;

    uboot_reloc_mem_addr = 0xFC000000;
    uboot_reloc_mem_size = 32*MB;
    #
    # Other constant sizes
    #
    linux_ddr_ipc_size = 1*MB;
    linux_ddr_resource_table_size = 1*KB;

    #
    # MSMC memory allocation for various CPUs
    #
    dmsc_msmc_size = 64*KB;
    mpu1_msmc_addr = msmc_mem_addr;
    mpu1_msmc_size = 128*KB;
    msmc_placeholder_addr = mpu1_msmc_addr + mpu1_msmc_size;
    misc_msmc_stack_size = 32*KB;
    msmc_placeholder_size = 8*MB - mpu1_msmc_size - dmsc_msmc_size - misc_msmc_stack_size;
    dmsc_msmc_addr = msmc_placeholder_addr + msmc_placeholder_size + misc_msmc_stack_size;

    #
    # C7x L1, L2 memory allocation
    # L1 - 32KB $, 16KB SRAM
    # L2 - 64KB $, 448KB SRAM
    c7x_1_l2_addr = 0x64800000;
    c7x_1_l2_size = (512 - 64)*KB;
    c7x_1_l1_addr = 0x64E00000;
    c7x_1_l1_size = 16*KB;
    c7x_1_msmc_addr = 0x68000000;
    c7x_1_msmc_size = 3*MB;

    #
    # C7x L1, L2 memory allocation
    # L1 - 32KB $, 16KB SRAM
    # L2 - 64KB $, 448KB SRAM
    c7x_2_l2_addr = 0x65800000;
    c7x_2_l2_size = (512 - 64)*KB;
    c7x_2_l1_addr = 0x65E00000;
    c7x_2_l1_size = 16*KB;
    c7x_2_msmc_addr = 0x69000000;
    c7x_2_msmc_size = 3*MB;

    #
    # C7x L1, L2 memory allocation
    # L1 - 32KB $, 16KB SRAM
    # L2 - 64KB $, 448KB SRAM
    c7x_3_l2_addr = 0x66800000;
    c7x_3_l2_size = (512 - 64)*KB;
    c7x_3_l1_addr = 0x66E00000;
    c7x_3_l1_size = 16*KB;
    c7x_3_msmc_addr = 0x6A000000;
    c7x_3_msmc_size = 3*MB;

    #
    # C7x L1, L2 memory allocation
    # L1 - 32KB $, 16KB SRAM
    # L2 - 64KB $, 448KB SRAM
    c7x_4_l2_addr = 0x67800000;
    c7x_4_l2_size = (512 - 64)*KB;
    c7x_4_l1_addr = 0x67E00000;
    c7x_4_l1_size = 16*KB;
    c7x_4_msmc_addr = 0x6B000000;
    c7x_4_msmc_size = 3*MB;

    #
    # Main OCRAM memory allocation
    #
    mcu2_0_main_ocram_addr = main_ocram_mem_addr;
    mcu2_0_main_ocram_addr_phys = main_ocram_mem_addr_phys;
    mcu2_0_main_ocram_size = 256*KB;

    mcu2_1_main_ocram_addr = mcu2_0_main_ocram_addr + mcu2_0_main_ocram_size;
    mcu2_1_main_ocram_addr_phys = mcu2_0_main_ocram_addr_phys + mcu2_0_main_ocram_size;
    mcu2_1_main_ocram_size = 256*KB;

    mcu4_0_main_ocram_addr = mcu2_1_main_ocram_addr + mcu2_1_main_ocram_size;
    mcu4_0_main_ocram_addr_phys = mcu2_1_main_ocram_addr_phys + mcu2_1_main_ocram_size;
    mcu4_0_main_ocram_size = 512*KB;

    #
    # DDR memory allocation for various CPUs
    #
    mcu1_0_ddr_ipc_addr = ddr_mem_addr;
    mcu1_0_ddr_resource_table_addr = mcu1_0_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu1_0_ddr_addr = mcu1_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu1_0_ddr_size = 16*MB - (mcu1_0_ddr_addr-mcu1_0_ddr_ipc_addr);

    mcu1_1_ddr_ipc_addr = mcu1_0_ddr_addr + mcu1_0_ddr_size;
    mcu1_1_ddr_resource_table_addr = mcu1_1_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu1_1_ddr_addr = mcu1_1_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu1_1_ddr_size = 16*MB - (mcu1_1_ddr_addr-mcu1_1_ddr_ipc_addr);

    mcu2_0_ddr_ipc_addr = mcu1_1_ddr_addr + mcu1_1_ddr_size;
    mcu2_0_ddr_resource_table_addr = mcu2_0_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu2_0_ddr_addr = mcu2_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu2_0_ddr_size = 32*MB - (mcu2_0_ddr_addr-mcu2_0_ddr_ipc_addr);

    mcu2_1_ddr_ipc_addr = mcu2_0_ddr_addr + mcu2_0_ddr_size;
    mcu2_1_ddr_resource_table_addr = mcu2_1_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu2_1_ddr_addr = mcu2_1_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu2_1_ddr_size = 16*MB - (mcu2_1_ddr_addr-mcu2_1_ddr_ipc_addr);

    mcu3_0_ddr_ipc_addr = mcu2_1_ddr_addr + mcu2_1_ddr_size;
    mcu3_0_ddr_resource_table_addr = mcu3_0_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu3_0_ddr_addr = mcu3_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu3_0_ddr_size = 16*MB - (mcu3_0_ddr_addr-mcu3_0_ddr_ipc_addr);

    mcu3_1_ddr_ipc_addr = mcu3_0_ddr_addr + mcu3_0_ddr_size;
    mcu3_1_ddr_resource_table_addr = mcu3_1_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu3_1_ddr_addr = mcu3_1_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu3_1_ddr_size = 16*MB - (mcu3_1_ddr_addr-mcu3_1_ddr_ipc_addr);

    mcu4_0_ddr_ipc_addr = mcu3_1_ddr_addr + mcu3_1_ddr_size;
    mcu4_0_ddr_resource_table_addr = mcu4_0_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu4_0_ddr_addr = mcu4_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu4_0_ddr_size = 16*MB - (mcu4_0_ddr_addr-mcu4_0_ddr_ipc_addr);

    mcu4_1_ddr_ipc_addr = mcu4_0_ddr_addr + mcu4_0_ddr_size;
    mcu4_1_ddr_resource_table_addr = mcu4_1_ddr_ipc_addr + linux_ddr_ipc_size;
    mcu4_1_ddr_addr = mcu4_1_ddr_resource_table_addr + linux_ddr_resource_table_size;
    mcu4_1_ddr_size = 16*MB - (mcu4_1_ddr_addr-mcu4_1_ddr_ipc_addr);

    # Hardcoding this value, as this cannot be different from IPC echo test value
    ipc_vring_mem_addr = 0xAC000000;
    ipc_vring_mem_size = 48*MB;

    app_log_mem_addr = ipc_vring_mem_addr + ipc_vring_mem_size;
    app_log_mem_size = 256*KB;

    tiovx_obj_desc_mem_addr = app_log_mem_addr + app_log_mem_size;
    tiovx_obj_desc_mem_size = 32*MB - app_log_mem_size;

    app_fileio_mem_addr = tiovx_obj_desc_mem_addr + tiovx_obj_desc_mem_size;
    app_fileio_mem_size = 4*MB;

    tiovx_log_rt_mem_addr = app_fileio_mem_addr + app_fileio_mem_size;
    tiovx_log_rt_mem_size = 16*MB - app_fileio_mem_size;

    c7x_1_ddr_ipc_addr = tiovx_log_rt_mem_addr + tiovx_log_rt_mem_size;
    c7x_1_ddr_resource_table_addr = c7x_1_ddr_ipc_addr + linux_ddr_ipc_size;
    c7x_1_ddr_boot_addr = c7x_1_ddr_resource_table_addr + 1*MB;
    c7x_1_ddr_boot_size = 1*KB;
    c7x_1_ddr_vecs_addr = c7x_1_ddr_resource_table_addr + 3*MB;
    c7x_1_ddr_vecs_size = 16*KB;
    c7x_1_ddr_secure_vecs_addr = c7x_1_ddr_resource_table_addr + 5*MB;
    c7x_1_ddr_secure_vecs_size = 16*KB;
    c7x_1_ddr_addr = c7x_1_ddr_resource_table_addr + 7*MB;
    c7x_1_ddr_size = 24*MB;

    c7x_2_ddr_ipc_addr = c7x_1_ddr_addr + c7x_1_ddr_size;
    c7x_2_ddr_resource_table_addr = c7x_2_ddr_ipc_addr + linux_ddr_ipc_size;
    c7x_2_ddr_boot_addr = c7x_2_ddr_resource_table_addr + 1*MB;
    c7x_2_ddr_boot_size = 1*KB;
    c7x_2_ddr_vecs_addr = c7x_2_ddr_resource_table_addr + 3*MB;
    c7x_2_ddr_vecs_size = 16*KB;
    c7x_2_ddr_secure_vecs_addr = c7x_2_ddr_resource_table_addr + 5*MB;
    c7x_2_ddr_secure_vecs_size = 16*KB;
    c7x_2_ddr_addr = c7x_2_ddr_resource_table_addr + 7*MB;
    c7x_2_ddr_size = 24*MB;

    c7x_3_ddr_ipc_addr = c7x_2_ddr_addr + c7x_2_ddr_size;
    c7x_3_ddr_resource_table_addr = c7x_3_ddr_ipc_addr + linux_ddr_ipc_size;
    c7x_3_ddr_boot_addr = c7x_3_ddr_resource_table_addr + 1*MB;
    c7x_3_ddr_boot_size = 1*KB;
    c7x_3_ddr_vecs_addr = c7x_3_ddr_resource_table_addr + 3*MB;
    c7x_3_ddr_vecs_size = 16*KB;
    c7x_3_ddr_secure_vecs_addr = c7x_3_ddr_resource_table_addr + 5*MB;
    c7x_3_ddr_secure_vecs_size = 16*KB;
    c7x_3_ddr_addr = c7x_3_ddr_resource_table_addr + 7*MB;
    c7x_3_ddr_size = 24*MB;

    c7x_4_ddr_ipc_addr = c7x_3_ddr_addr + c7x_3_ddr_size;
    c7x_4_ddr_resource_table_addr = c7x_4_ddr_ipc_addr + linux_ddr_ipc_size;
    c7x_4_ddr_boot_addr = c7x_4_ddr_resource_table_addr + 1*MB;
    c7x_4_ddr_boot_size = 1*KB;
    c7x_4_ddr_vecs_addr = c7x_4_ddr_resource_table_addr + 3*MB;
    c7x_4_ddr_vecs_size = 16*KB;
    c7x_4_ddr_secure_vecs_addr = c7x_4_ddr_resource_table_addr + 5*MB;
    c7x_4_ddr_secure_vecs_size = 16*KB;
    c7x_4_ddr_addr = c7x_4_ddr_resource_table_addr + 7*MB;
    c7x_4_ddr_size = 24*MB;

    #
    # DDR memory allocation for various shared memories
    #

    mcu1_0_ddr_local_heap_addr = c7x_4_ddr_addr + c7x_4_ddr_size;
    mcu1_0_ddr_local_heap_size = 8*MB;
    mcu1_1_ddr_local_heap_addr = mcu1_0_ddr_local_heap_addr + mcu1_0_ddr_local_heap_size;
    mcu1_1_ddr_local_heap_size = 8*MB;
    mcu2_0_ddr_local_heap_addr = mcu1_1_ddr_local_heap_addr + mcu1_1_ddr_local_heap_size;
    mcu2_0_ddr_local_heap_size = 128*MB;
    mcu2_1_ddr_local_heap_addr = mcu2_0_ddr_local_heap_addr + mcu2_0_ddr_local_heap_size;
    mcu2_1_ddr_local_heap_size = 16*MB;
    mcu3_0_ddr_local_heap_addr = mcu2_1_ddr_local_heap_addr + mcu2_1_ddr_local_heap_size;
    mcu3_0_ddr_local_heap_size = 8*MB;
    mcu3_1_ddr_local_heap_addr = mcu3_0_ddr_local_heap_addr + mcu3_0_ddr_local_heap_size;
    mcu3_1_ddr_local_heap_size = 8*MB;
    mcu4_0_ddr_local_heap_addr = mcu3_1_ddr_local_heap_addr + mcu3_1_ddr_local_heap_size;
    mcu4_0_ddr_local_heap_size = 8*MB;
    mcu4_1_ddr_local_heap_addr = mcu4_0_ddr_local_heap_addr + mcu4_0_ddr_local_heap_size;
    mcu4_1_ddr_local_heap_size = 8*MB;

    ddr_intercore_eth_desc_addr = mcu4_1_ddr_local_heap_addr + mcu4_1_ddr_local_heap_size;
    ddr_intercore_eth_desc_size = 8*MB;

    ddr_intercore_eth_data_addr = ddr_intercore_eth_desc_addr + ddr_intercore_eth_desc_size;
    ddr_intercore_eth_data_size = 24*MB;

    # Shared memory for DMA Buf FD carveout
    ddr_shared_mem_addr = ddr_intercore_eth_data_addr + ddr_intercore_eth_data_size;
    ddr_shared_mem_size = SHARED_MEM_SIZE - uboot_reloc_mem_size;

    # C7x 1 Persistent DDR
    c7x_1_ddr_local_heap_non_cacheable_addr = ddr_mem_addr_hi;
    c7x_1_ddr_local_heap_non_cacheable_addr_phys = ddr_mem_addr_hi_phys;
    c7x_1_ddr_local_heap_non_cacheable_size = 32*MB;
    c7x_1_ddr_local_heap_addr = c7x_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
    c7x_1_ddr_local_heap_addr_phys = c7x_1_ddr_local_heap_non_cacheable_addr_phys + c7x_1_ddr_local_heap_non_cacheable_size;
    c7x_1_ddr_local_heap_size = 32*MB;
    total_c7x_1_local_ddr = c7x_1_ddr_local_heap_non_cacheable_size + c7x_1_ddr_local_heap_size;

    # C7x 1 Scratch DDR
    c7x_1_ddr_scratch_non_cacheable_addr = c7x_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
    c7x_1_ddr_scratch_non_cacheable_addr_phys = c7x_1_ddr_local_heap_addr_phys + c7x_1_ddr_local_heap_size;
    c7x_1_ddr_scratch_non_cacheable_size = 32*MB;
    c7x_1_ddr_scratch_addr = c7x_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
    c7x_1_ddr_scratch_addr_phys = c7x_1_ddr_scratch_non_cacheable_addr_phys + c7x_1_ddr_scratch_non_cacheable_size;
    c7x_1_ddr_scratch_size = 32*MB;
    total_c7x_1_scratch_ddr = c7x_1_ddr_scratch_non_cacheable_size + c7x_1_ddr_scratch_size

    total_c7x_1_ddr = total_c7x_1_local_ddr + total_c7x_1_scratch_ddr

    # C7x 2 Persistent DDR
    c7x_2_ddr_local_heap_non_cacheable_addr = ddr_mem_addr_hi;
    c7x_2_ddr_local_heap_non_cacheable_addr_phys = c7x_1_ddr_scratch_addr_phys + c7x_1_ddr_scratch_size;
    c7x_2_ddr_local_heap_non_cacheable_size = 32*MB;
    c7x_2_ddr_local_heap_addr = c7x_2_ddr_local_heap_non_cacheable_addr + c7x_2_ddr_local_heap_non_cacheable_size;
    c7x_2_ddr_local_heap_addr_phys = c7x_2_ddr_local_heap_non_cacheable_addr_phys + c7x_2_ddr_local_heap_non_cacheable_size;
    c7x_2_ddr_local_heap_size = 32*MB;
    total_c7x_2_local_ddr = c7x_2_ddr_local_heap_non_cacheable_size + c7x_2_ddr_local_heap_size

    # C7x 2 Scratch DDR
    c7x_2_ddr_scratch_non_cacheable_addr = c7x_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size;
    c7x_2_ddr_scratch_non_cacheable_addr_phys = c7x_2_ddr_local_heap_addr_phys + c7x_2_ddr_local_heap_size;
    c7x_2_ddr_scratch_non_cacheable_size = 32*MB;
    c7x_2_ddr_scratch_addr = c7x_2_ddr_scratch_non_cacheable_addr + c7x_2_ddr_scratch_non_cacheable_size;
    c7x_2_ddr_scratch_addr_phys = c7x_2_ddr_scratch_non_cacheable_addr_phys + c7x_2_ddr_scratch_non_cacheable_size;
    c7x_2_ddr_scratch_size = 32*MB;
    total_c7x_2_scratch_ddr = c7x_2_ddr_scratch_non_cacheable_size + c7x_2_ddr_scratch_size

    total_c7x_2_ddr = total_c7x_2_local_ddr + total_c7x_2_scratch_ddr

    # C7x 3 Persistent DDR
    c7x_3_ddr_local_heap_non_cacheable_addr = ddr_mem_addr_hi;
    c7x_3_ddr_local_heap_non_cacheable_addr_phys = c7x_2_ddr_scratch_addr_phys + c7x_2_ddr_scratch_size;
    c7x_3_ddr_local_heap_non_cacheable_size = 32*MB;
    c7x_3_ddr_local_heap_addr = c7x_3_ddr_local_heap_non_cacheable_addr + c7x_3_ddr_local_heap_non_cacheable_size;
    c7x_3_ddr_local_heap_addr_phys = c7x_3_ddr_local_heap_non_cacheable_addr_phys + c7x_3_ddr_local_heap_non_cacheable_size;
    c7x_3_ddr_local_heap_size = 32*MB;
    total_c7x_3_local_ddr = c7x_3_ddr_local_heap_non_cacheable_size + c7x_3_ddr_local_heap_size
    # C7x 3 Scratch DDR
    c7x_3_ddr_scratch_non_cacheable_addr = c7x_3_ddr_local_heap_addr + c7x_3_ddr_local_heap_size;
    c7x_3_ddr_scratch_non_cacheable_addr_phys = c7x_3_ddr_local_heap_addr_phys + c7x_3_ddr_local_heap_size;
    c7x_3_ddr_scratch_non_cacheable_size = 32*MB;
    c7x_3_ddr_scratch_addr = c7x_3_ddr_scratch_non_cacheable_addr + c7x_3_ddr_scratch_non_cacheable_size;
    c7x_3_ddr_scratch_addr_phys = c7x_3_ddr_scratch_non_cacheable_addr_phys + c7x_3_ddr_scratch_non_cacheable_size;
    c7x_3_ddr_scratch_size = 32*MB;
    total_c7x_3_scratch_ddr = c7x_3_ddr_scratch_non_cacheable_size + c7x_3_ddr_scratch_size

    total_c7x_3_ddr = total_c7x_3_local_ddr + total_c7x_3_scratch_ddr

    # C7x 4 Persistent DDR
    c7x_4_ddr_local_heap_non_cacheable_addr = ddr_mem_addr_hi;
    c7x_4_ddr_local_heap_non_cacheable_addr_phys = c7x_3_ddr_scratch_addr_phys + c7x_3_ddr_scratch_size;
    c7x_4_ddr_local_heap_non_cacheable_size = 32*MB;
    c7x_4_ddr_local_heap_addr = c7x_4_ddr_local_heap_non_cacheable_addr + c7x_4_ddr_local_heap_non_cacheable_size;
    c7x_4_ddr_local_heap_addr_phys = c7x_4_ddr_local_heap_non_cacheable_addr_phys + c7x_4_ddr_local_heap_non_cacheable_size;
    c7x_4_ddr_local_heap_size = 32*MB;
    total_c7x_4_local_ddr = c7x_4_ddr_local_heap_non_cacheable_size + c7x_4_ddr_local_heap_size

    # C7x 4 Scratch DDR
    c7x_4_ddr_scratch_non_cacheable_addr = c7x_4_ddr_local_heap_addr + c7x_4_ddr_local_heap_size;
    c7x_4_ddr_scratch_non_cacheable_addr_phys = c7x_4_ddr_local_heap_addr_phys + c7x_4_ddr_local_heap_size;
    c7x_4_ddr_scratch_non_cacheable_size = 32*MB;
    c7x_4_ddr_scratch_addr = c7x_4_ddr_scratch_non_cacheable_addr + c7x_4_ddr_scratch_non_cacheable_size;
    c7x_4_ddr_scratch_addr_phys = c7x_4_ddr_scratch_non_cacheable_addr_phys + c7x_4_ddr_scratch_non_cacheable_size;
    c7x_4_ddr_scratch_size = 32*MB;
    total_c7x_4_scratch_ddr = c7x_4_ddr_scratch_non_cacheable_size + c7x_4_ddr_scratch_size

    total_c7x_4_ddr = total_c7x_4_local_ddr + total_c7x_4_scratch_ddr

    total_c7x_ddr = total_c7x_1_ddr + total_c7x_2_ddr + total_c7x_3_ddr + total_c7x_4_ddr

  • This section is the content of the gen_linker_mem_map.py file, which captures a configurable section.

  • Hi,

    The memory changes looks correct. It did not cross to 64bit region because I see that you have reduced the SHARED_MEM to 480MB and uboot relloc size to 32MB.

    Is this changes done by you? because these are not the defualt values of SDK.

    Also, the C7x heap and scratch sizes are reduced to 32MB from 128MB in SDK.

    Running my test program produces the following error:

            
            

    Could you let me know what this test program is and can you share me full logs of the boot, remote core logs and your application?

    Please provide it in the form of a file (not screenshots).

    You could upload a file by drag - drop into the e2e replies.

    Regards,

    Nikhil

  • HI

    The part of the memory modification you pointed out is my change, because the total capacity of the DDR I use is 8GB.

    system_boot_log-IPC_fail.txt

    This file is the full logs.

  • Hi,

    I see a gap between these 2 regions. Here for RAT, we are giving both the regions. I'm suspecting the failing of RAT because of this GAP. Could you try to remove this gap?

    Also, below are the last logs from MCU2_0 

    [MCU2_0] 3.964102 s: set TCA9539 pin is output! *****
    [MCU2_0] 4.063475 s: **** appGMSL loop High !
    [MCU2_0] 4.163913 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0] 4.164375 s: **** read TCA9539_1, 0x2 val:0x03

    This seems to be custom implementation. Could you check if this is the cause for the same?

    The current issue here is that all the R5 cores are hung and the IPC initialization is not yet happened. You would have to check the exact region of Hang either through more logs or by connecting CCS.

    Regards,

    Nikhil

  • Hi,

    After I restore DDR_SHARED_MEM and UBOOT_RELOC_MEM to the initial SDK values, I have to modify the MCU heap memory to the initial SDK values, Otherwise, the DDR_SHARED_MEM address range will overlap the DDR_C7X_LOCAL_HEAP_NON_CACHEABLE address range.

    The log in your screenshot is my custom part, I tried to comment out these have no effect on the test results.

    In addition, the modification of DDR_SHARED_MEM and UBOOT_RELOC_MEM was done early and did not cause IPC communication failures. On this basis, after I modified the size of DDR_MCU2_0_LOCLA_HEAP, the IPC communication failure occurred.

    Could it be that something else was wrong that caused the problem?

  • Hi,

    On this basis, after I modified the size of DDR_MCU2_0_LOCLA_HEAP, the IPC communication failure occurred.

    The issue here is not ipc communication failure. 

    The main reason for the ipc error is because the R5 cores are stuck / hang before IpcInit() from the vision_apps remote core logs. So we would have to check where exactly the R5 cores are hung.

    We could use CCS to identify the same.

    The last log from MCU2_0 is.

    [MCU2_0] 3.964102 s: set TCA9539 pin is output! *****
    [MCU2_0] 4.063475 s: **** appGMSL loop High !
    [MCU2_0] 4.163913 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0] 4.164375 s: **** read TCA9539_1, 0x2 val:0x03

    Could please let me know what this change is? 

    Regards,

    Nikhil

  • I'm sorry, I misunderstood you earlier.
    On the MCU2_0 core, I created an additional thread: appGMSL, and the log you see is the task and output of this thread.

    The change I made was to comment out the thread.

    According to what you said, IPC communication may be caused by R5 core suspension. I have done the following tests:

    while(1) is added to both thread appMain and thread appGMSL.

    From running the log, you can see that while(1) of the appGMSL thread is always executing, but appMain does not print the log.

    This seems abnormal.

    Here are the main.c files for the log and MCU2_0 for this test

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     * OF THE POSSIBILITY OF SUCH DAMAGE.
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     */
    
    #include <app.h>
    #include <utils/console_io/include/app_log.h>
    #include <utils/ethfw/include/app_ethfw.h>
    #include <utils/rtos/include/app_rtos.h>
    #include <stdio.h>
    #include <string.h>
    #include <ti/osal/osal.h>
    #include <app_ipc_rsctable.h>
    #include "app_cfg_mcu2_0.h"
    #include <utils/perf_stats/include/app_perf_stats.h>
    
    #include "GPIO_board.h"
    #include "sedes_i2c.h"
    
    sedes_params GMSL_obj;
    SemaphoreP_Params       GMSL_semPrms;
    SemaphoreP_Handle       GMSL_start_hdl;
    
    static void appMain(void* arg0, void* arg1)
    {
    	uint8_t ret;
    	uint8_t index;
    	
        appInit();
        appRun();
    
        #if 1
        while(1)
        {
        	appLogPrintf("****** loop *****\n");
            appLogWaitMsecs(1000u);
    		
    		index ++;
    		ret = GPIO_read(GPIO_TEST1);
    		appLogPrintf("GPIO_read GPIO_TEST1 value:%d\n", ret);
    
    		ret = GPIO_read(GPIO_TEST2);
    		appLogPrintf("GPIO_read GPIO_TEST2 value:%d\n", ret);
    		
    		if(index % 2) {
    			GPIO_write(GPIO_TEST1, GPIO_PIN_VAL_LOW);
    			GPIO_write(GPIO_TEST2, GPIO_PIN_VAL_HIGH);
    		} else {
    			GPIO_write(GPIO_TEST2, GPIO_PIN_VAL_LOW);
    			GPIO_write(GPIO_TEST1, GPIO_PIN_VAL_HIGH);
    		}
    		
        }
        #else
        appDeInit();
        #endif
    }
    
    static void appGMSL(void* arg0, void* arg1)
    {
    	int32_t retVal;
    
        Board_initCfg boardCfg;
    	appLogPrintf("****** appGMSL Enter *****\n");
    
        /** @brief Create Semaphore  */
        SemaphoreP_Params_init(&GMSL_semPrms);
        GMSL_semPrms.mode = SemaphoreP_Mode_BINARY;
        GMSL_start_hdl = SemaphoreP_create(0U, &GMSL_semPrms);
    
        if(NULL == GMSL_start_hdl)
        {
            printf(" Sem create failed\r\n");
        }
    
        boardCfg = BOARD_INIT_PINMUX_CONFIG |
            BOARD_INIT_MODULE_CLOCK;
        // boardCfg = BOARD_INIT_PINMUX_CONFIG |
        //     BOARD_INIT_MODULE_CLOCK |
        //     BOARD_INIT_UART_STDIO;
    
        Board_init(boardCfg);
    	GPIO_init();
    
    	/* Initialize I2C Driver */
        I2C_init_config();
    	
        /* Initializes the I2C */
        I2C_init();
        retVal = I2C_inst_setup();
    	if(retVal == -1){
    		appLogPrintf("I2C_inst_setup error! \n");
    		return;
    	}
    
        uint8_t val_0;
    	uint8_t val_1;
    	
    	sedes_8reg_read((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_0_I2C5_ADDR, 0x6, &val_0);
    	sedes_8reg_read((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_1_I2C5_ADDR, 0x6, &val_1);
    	appLogPrintf("**** read TCA9539_0, 0x6 val:0x%02x\n", val_0);
    	appLogPrintf("**** read TCA9539_1, 0x6 val:0x%02x\n", val_1);
    	appLogWaitMsecs(100u);
    
        val_0 = 0x07;
    	val_1 = 0xFC; // ok
    	// val_1 = 0xF8; // ok
    	// val_1 = 0xF7; // ok
    	// val_1 = 0xF3; // ok
    	// val_1 = 0xF1; // ok
    	// val_1 = 0xF0; // fail
    	sedes_8reg_write((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_0_I2C5_ADDR, 0x6, val_0);
    	sedes_8reg_write((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_1_I2C5_ADDR, 0x6, val_1);
    	appLogPrintf("set TCA9539 pin is output! ***** \n");
    	appLogWaitMsecs(100u);
    
    	val_0 = 0xF8;
    	val_1 = 0x03;
    	appLogPrintf("**** appGMSL loop High !\n");
    	sedes_8reg_write((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_0_I2C5_ADDR, 0x2, val_0);
    	sedes_8reg_write((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_1_I2C5_ADDR, 0x2, val_1);
    	appLogWaitMsecs(100u);
    
    	SemaphoreP_post(GMSL_start_hdl);
    	while(1)
        {
        	sedes_8reg_read((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_0_I2C5_ADDR, 0x2, &val_0);
    		appLogPrintf("**** read TCA9539_0, 0x2 val:0x%02x\n", val_0);
    		sedes_8reg_read((void *)GMSL_obj.i2cHandle_TCA9539, TCA9539_1_I2C5_ADDR, 0x2, &val_1);
    		appLogPrintf("**** read TCA9539_1, 0x2 val:0x%02x\n", val_1);
    		appLogWaitMsecs(1000u);
        }
    }
    
    void StartupEmulatorWaitFxn (void)
    {
        volatile uint32_t enableDebug = 0;
        do
        {
        }while (enableDebug);
    }
    
    static uint8_t gTskStackMain[8*1024]
    __attribute__ ((section(".bss:taskStackSection")))
    __attribute__ ((aligned(8192)))
        ;
    static uint8_t gTskStackSDES[32*1024]
    __attribute__ ((section(".bss:taskStackSection")))
    __attribute__ ((aligned(8192)))
        ;
    
    int main(void)
    {
        app_rtos_task_params_t tskParams;
        app_rtos_task_handle_t task;
    
    	app_rtos_task_params_t GMSL_tskPar;
        app_rtos_task_handle_t GMSL_task;
    
    #ifdef ENABLE_ETHFW
        appEthFwEarlyInit();
    #endif
    
        /* This is for debug purpose - see the description of function header */
        StartupEmulatorWaitFxn();
    
        OS_init();
    
        appPerfStatsInit();
    
        appRtosTaskParamsInit(&tskParams);
        tskParams.priority = 8u;
        tskParams.stack = gTskStackMain;
        tskParams.stacksize = sizeof (gTskStackMain);
        tskParams.taskfxn = &appMain;
        task = appRtosTaskCreate(&tskParams);
        if(NULL == task)
        {
        	appLogPrintf("appMain task is null!\n");
            OS_stop();
        }
    
    	TaskP_Params_init(&GMSL_tskPar);
        GMSL_tskPar.priority = 9u;
        GMSL_tskPar.stack = gTskStackSDES;
        GMSL_tskPar.stacksize = sizeof (gTskStackSDES);
    	GMSL_tskPar.taskfxn = &appGMSL;
        GMSL_task = appRtosTaskCreate(&GMSL_tskPar);
        if(NULL == GMSL_task)
        {
        	appLogPrintf("GMSL task is null!\n");
            OS_stop();
        }
    
        OS_start();
    
        return 0;
    }
    
    uint32_t appGetDdrSharedHeapSize()
    {
        return DDR_SHARED_MEM_SIZE;
    
    }
    
    uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
                                          uint32_t chNum,
                                          void *appData)
    {
    
      return (uint64_t)virtAddr;
    }
    
    uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
    {
        uint64_t target_ptr;
    
        /* Note: I think this is correct but needs review */
        if ( ((uint64_t)shared_ptr >= DDR_SHARED_MEM_PHYS_ADDR) &&
             ((uint64_t)shared_ptr < (DDR_SHARED_MEM_PHYS_ADDR+DDR_SHARED_MEM_PHYS_SIZE)) )
        {
            if (DDR_SHARED_MEM_PHYS_ADDR >= DDR_SHARED_MEM_ADDR)
            {
                target_ptr = (uint64_t)shared_ptr - (DDR_SHARED_MEM_PHYS_ADDR - DDR_SHARED_MEM_ADDR);
            }
            else
            {
                target_ptr = (uint64_t)shared_ptr + (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
            }
        }
        else
        {
            target_ptr = (uint64_t)shared_ptr;
        }
    
        return target_ptr;
    }
    
    IPC fail log.txt

    Finally, what does CCS stand for? I didn't understand this.

    Thanks.

  • Hi,

    Finally, what does CCS stand for? I didn't understand this.

    CCS is Code Composer Studio, a tool which we use to debug on the EVM using the xds110.

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/09_01_00_06/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j721e.html

    On the MCU2_0 core, I created an additional thread: appGMSL, and the log you see is the task and output of this thread.

    I see. Do you see the hang in MCU2_0 without creation of this task? (i.e. Does MCU2_0 reaches the "App Run.. Done" log)

    Do you have a memory configuration where MCU2_0 is booting completely? If yes, could you share that too so that we could look at the delta.

    Regards,

    Nikhil

  • Hi
    When the appGMSL thread without  created, MCU2_0 is still in hang , and MCU2_0 logs only APP:Init... !!!!!!!!!

    You can view the log file:

    j784s4-evm login: [   16.553372] platform main-r5fss-cpsw9g-virt-mac0: deferred probe pending
    [   16.560076] platform regulator-sd: deferred probe pending
    [   16.565466] platform regulator-dp0-prw: deferred probe pending
    [   16.571290] platform regulator-dp1-prw: deferred probe pending
    [   16.577111] platform 2900000.pcie: deferred probe pending
    [   16.582497] platform 4800000.dsi: deferred probe pending
    [   16.587796] platform a000000.dp-bridge: deferred probe pending
    [   16.593615] platform dp0-connector: deferred probe pending
    [   16.599087] platform 2910000.pcie: deferred probe pending
    [   16.604473] platform main-r5fss-cpsw9g-virt-mac1: deferred probe pending
    root
    [   17.742946] audit: type=1006 audit(1708486359.250:10): pid=723 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=3 res=1
    [   17.755325] audit: type=1300 audit(1708486359.250:10): arch=c00000b7 syscall=64 success=yes exit=1 a0=8 a1=ffffc20f7618 a2=1 a3=ffff93523020 items=0 ppid=1 pid=723 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="(systemd)" exe="/lib/systemd/systemd" key=(null)
    [   17.781941] audit: type=1327 audit(1708486359.250:10): proctitle="(systemd)"
    [   17.789023] audit: type=1334 audit(1708486359.258:11): prog-id=11 op=LOAD
    [   17.795827] audit: type=1300 audit(1708486359.258:11): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffd6304f70 a2=78 a3=0 items=0 ppid=1 pid=723 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null)
    [   17.821163] audit: type=1327 audit(1708486359.258:11): proctitle="(systemd)"
    [   17.828212] audit: type=1334 audit(1708486359.266:12): prog-id=11 op=UNLOAD
    [   17.835166] audit: type=1334 audit(1708486359.266:13): prog-id=12 op=LOAD
    [   17.841950] audit: type=1300 audit(1708486359.266:13): arch=c00000b7 syscall=280 success=yes exit=8 a0=5 a1=ffffd6305010 a2=78 a3=0 items=0 ppid=1 pid=723 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=3 comm="systemd" exe="/lib/systemd/systemd" key=(null)
    [   17.867279] audit: type=1327 audit(1708486359.266:13): proctitle="(systemd)"
    root@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh
    root@j784s4-evm:~# [MCU2_0]      4.020420 s: CIO: Init ... Done !!!
    [MCU2_0]      4.020472 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0]      4.020496 s: CPU is running FreeRTOS
    [MCU2_0]      4.020511 s: APP: Init ... !!!
    [MCU2_0]      4.020539 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [MCU2_1]      4.040665 s: CIO: Init ... Done !!!
    [MCU2_1]      4.040717 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_1]      4.040743 s: CPU is running FreeRTOS
    [MCU2_1]      4.040758 s: APP: Init ... !!!
    [MCU2_1]      4.040787 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [MCU3_0]      4.084905 s: CIO: Init ... Done !!!
    [MCU3_0]      4.084955 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_0]      4.084978 s: CPU is running FreeRTOS
    [MCU3_0]      4.084993 s: APP: Init ... !!!
    [MCU3_0]      4.085012 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [MCU3_1]      4.129612 s: CIO: Init ... Done !!!
    [MCU3_1]      4.129664 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_1]      4.129688 s: CPU is running FreeRTOS
    [MCU3_1]      4.129705 s: APP: Init ... !!!
    [MCU3_1]      4.129725 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [MCU4_0]      4.200126 s: CIO: Init ... Done !!!
    [MCU4_0]      4.200175 s: ### CPU Frequency = 1000000000 Hz
    [MCU4_0]      4.200201 s: CPU is running FreeRTOS
    [MCU4_0]      4.200217 s: APP: Init ... !!!
    [MCU4_0]      4.200247 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [MCU4_1]      4.233948 s: CIO: Init ... Done !!!
    [MCU4_1]      4.234000 s: ### CPU Frequency = 1000000000 Hz
    [MCU4_1]      4.234024 s: CPU is running FreeRTOS
    [MCU4_1]      4.234040 s: APP: Init ... !!!
    [MCU4_1]      4.234058 s: appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()
    [C7x_1 ]      4.600681 s: CIO: Init ... Done !!!
    [C7x_1 ]      4.600696 s: ### CPU Frequency = 1000000000 Hz
    [C7x_1 ]      4.600707 s: CPU is running FreeRTOS
    [C7x_1 ]      4.600716 s: APP: Init ... !!!
    [C7x_1 ]      4.600724 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      4.600834 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_1 ]      4.600848 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_1 ]      4.600859 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_1 ]      4.600869 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      4.600879 s: UDMA: Init ... !!!
    [C7x_1 ]      4.601778 s: UDMA: Init ... Done !!!
    [C7x_1 ]      4.601789 s: MEM: Init ... !!!
    [C7x_1 ]      4.601801 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_1 ]      4.601822 s: MEM: Init ... Done !!!
    [C7x_1 ]      4.601831 s: IPC: Init ... !!!
    [C7x_1 ]      4.601845 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_1 ]      4.601861 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_1 ]     13.708139 s: IPC: HLOS is ready !!!
    [C7x_1 ]     13.711452 s: IPC: Init ... Done !!!
    [C7x_1 ]     13.711467 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_2 ]      4.928636 s: CIO: Init ... Done !!!
    [C7x_2 ]      4.928653 s: ### CPU Frequency = 1000000000 Hz
    [C7x_2 ]      4.928665 s: CPU is running FreeRTOS
    [C7x_2 ]      4.928673 s: APP: Init ... !!!
    [C7x_2 ]      4.928681 s: SCICLIENT: Init ... !!!
    [C7x_2 ]      4.928789 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_2 ]      4.928803 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_2 ]      4.928813 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_2 ]      4.928824 s: SCICLIENT: Init ... Done !!!
    [C7x_2 ]      4.928833 s: UDMA: Init ... !!!
    [C7x_2 ]      4.929658 s: UDMA: Init ... Done !!!
    [C7x_2 ]      4.929669 s: MEM: Init ... !!!
    [C7x_2 ]      4.929680 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_2 ]      4.929700 s: MEM: Init ... Done !!!
    [C7x_2 ]      4.929709 s: IPC: Init ... !!!
    [C7x_2 ]      4.929723 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_2 ]      4.929739 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_2 ]     13.831157 s: IPC: HLOS is ready !!!
    [C7x_2 ]     13.834549 s: IPC: Init ... Done !!!
    [C7x_2 ]     13.834567 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_3 ]      5.243413 s: CIO: Init ... Done !!!
    [C7x_3 ]      5.243428 s: ### CPU Frequency = 1000000000 Hz
    [C7x_3 ]      5.243440 s: CPU is running FreeRTOS
    [C7x_3 ]      5.243449 s: APP: Init ... !!!
    [C7x_3 ]      5.243456 s: SCICLIENT: Init ... !!!
    [C7x_3 ]      5.243564 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_3 ]      5.243578 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_3 ]      5.243588 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_3 ]      5.243599 s: SCICLIENT: Init ... Done !!!
    [C7x_3 ]      5.243609 s: UDMA: Init ... !!!
    [C7x_3 ]      5.244440 s: UDMA: Init ... Done !!!
    [C7x_3 ]      5.244451 s: MEM: Init ... !!!
    [C7x_3 ]      5.244463 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_3 ]      5.244484 s: MEM: Init ... Done !!!
    [C7x_3 ]      5.244493 s: IPC: Init ... !!!
    [C7x_3 ]      5.244507 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_3 ]      5.244522 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_3 ]     13.931871 s: IPC: HLOS is ready !!!
    [C7x_3 ]     13.935286 s: IPC: Init ... Done !!!
    [C7x_3 ]     13.935303 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_4 ]      5.558411 s: CIO: Init ... Done !!!
    [C7x_4 ]      5.558427 s: ### CPU Frequency = 1000000000 Hz
    [C7x_4 ]      5.558438 s: CPU is running FreeRTOS
    [C7x_4 ]      5.558446 s: APP: Init ... !!!
    [C7x_4 ]      5.558454 s: SCICLIENT: Init ... !!!
    [C7x_4 ]      5.558562 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_4 ]      5.558576 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_4 ]      5.558587 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_4 ]      5.558598 s: SCICLIENT: Init ... Done !!!
    [C7x_4 ]      5.558608 s: UDMA: Init ... !!!
    [C7x_4 ]      5.559441 s: UDMA: Init ... Done !!!
    [C7x_4 ]      5.559453 s: MEM: Init ... !!!
    [C7x_4 ]      5.559464 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_4 ]      5.559485 s: MEM: Init ... Done !!!
    [C7x_4 ]      5.559494 s: IPC: Init ... !!!
    [C7x_4 ]      5.559508 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_4 ]      5.559523 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_4 ]     14.087418 s: IPC: HLOS is ready !!!
    [C7x_4 ]     14.090848 s: IPC: Init ... Done !!!
    [C7x_4 ]     14.090866 s: APP: Syncing with 10 CPUs ... !!!
    
    root@j784s4-evm:~#
    root@j784s4-evm:~# /opt/vision_apps/vx_app_kernel_practice.out
    APP: Init ... !!!
    MEM: Init ... !!!
    MEM: Initialized DMA HEAP (fd=5) !!!
    MEM: Init ... Done !!!
    IPC: Init ... !!!
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio4.rpmsg_chrdev.-1.13
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio6.rpmsg_chrdev.-1.13
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio7.rpmsg_chrdev.-1.13
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio8.rpmsg_chrdev.-1.13
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio9.rpmsg_chrdev.-1.13
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio10.rpmsg_chrdev.-1.13
    IPC: ERROR: Una[   57.675485] kauditd_printk_skb: 1 callbacks suppressed
    ble to create TX channels for CPU [mcu2_0] !!!
    IPC: ERROR: Unab[   57.675494] audit: type=1701 audit(1708486399.182:15): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=746 comm="vx_app_kernel_p" exe="/opt/vision_apps/vx_app_kernel_practice.out" sig=11 res=1
    le to create TX channels for CPU [mcu2_1] !!!
    IPC: ERROR: Unabl[   57.704162] audit: type=1334 audit(1708486399.210:16): prog-id=13 op=LOAD
    e to create TX channels for CPU [mcu3_0] !!!
    IPC: ERROR: Unable[   57.716420] audit: type=1334 audit(1708486399.222:17): prog-id=14 op=LOAD
     to create TX channels for CPU [mcu3_1] !!!
    IPC: ERROR: Unable to create TX channels for CPU [mcu4_0] !!!
    IPC: ERROR: Unable to create TX channels for CPU [mcu4_1] !!!
    IPC: Init ... Done !!!
    APP: ERROR: IPC init failed !!!
    REMOTE_SERVICE: Init ... !!!
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio4.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio6.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio7.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio8.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio9.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio10.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio0.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio2.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio3.rpmsg_chrdev.-1.21
    _rpmsg_char_find_ctrldev: could not find the matching rpmsg_ctrl device for virtio5.rpmsg_chrdev.-1.21
    REMOTE_SERVICE: Init ... Done !!!
        65.866423 s: GTC Frequency = 200 MHz
    APP: Init ... Done !!!
        65.872507 s:  VX_ZONE_INIT:Enabled
        65.872517 s:  VX_ZONE_ERROR:Enabled
        65.872524 s:  VX_ZONE_WARNING:Enabled
        65.878569 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
        65.886719 s:  VX_ZONE_INIT:[tivxHostInitLocal:101] Initialization Done for HOST !!!
    appInit done
    ******* kernel_practice_create Enter *********
    [MEM linux dma heap] appMemAlloc Enter
    =======local_params0.testdata0 = 1
    =======local_params0.testdata1 = 2
        65.904969 s:  VX_ZONE_ERROR:[vxSetNodeTarget:2182] Target ID is invalid for node node_2
    usecase_node_create_node_1 done
    kernel_practice_create done
    kernel_practice_verify done
    kernel_practice_run done
    kernel_practice_delete done
        65.904996 s:  VX_ZONE_INIT:[tivxHostDeInitLocal:115] De-Initialization Done for HOST !!!
        65.905018 s:  VX_ZONE_ERROR:[ownObjectDeInit:171] Is graph use failed, index: 0
        65.905025 s:  VX_ZONE_ERROR:[ownObjectDeInit:177] Is node use failed, index: 0
        65.905031 s:  VX_ZONE_ERROR:[ownObjectDeInit:183] Is kernel use failed, index: 0
        65.905037 s:  VX_ZONE_ERROR:[ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff
        65.905044 s:  VX_ZONE_ERROR:[ownObjectDeInit:196] Is user data object use failed, index: 0
        65.905053 s:  VX_ZONE_ERROR:[ownObjectDeInit:234] Is image use failed, index: 0
        65.905063 s:  VX_ZONE_ERROR:[ownObjectDeInit:282] Is error use failed, index: 0
        65.909414 s:  VX_ZONE_INIT:[tivxDeInitLocal:193] De-Initialization Done !!!
    APP: Deinit ... !!!
    REMOTE_SERVICE: Deinit ... !!!
    REMOTE_SERVICE: Deinit ... Done !!!
    IPC: Deinit ... !!!
    Segmentation fault (core dumped)
    root@j784s4-evm:~# [   59.132533] audit: type=1334 audit(1708486400.642:18): prog-id=14 op=UNLOAD
    [   59.139510] audit: type=1334 audit(1708486400.642:19): prog-id=13 op=UNLOAD
    

    I have the memory configuration to fully boot MCU2_0, just restore the local heap memory size allocated to R5 cores (mcux_x_ddr_local_heap_size) to the initial value (8M).

    In this case,SHARED_MEM_SIZE is 512MB (the initial value is 1024MB), and uboot_reloc_mem_size is 32MB (the initial value is 64MB).

     rtos log files:

    root@j784s4-evm:~# /opt/vision_apps/vision_apps_init.sh
    root@j784s4-evm:~# [MCU2_0]      4.128151 s: CIO: Init ... Done !!!
    [MCU2_0]      4.128183 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0]      4.128209 s: CPU is running FreeRTOS
    [MCU2_0]      4.128225 s: APP: Init ... !!!
    [MCU2_0]      4.128257 s: SCICLIENT: Init ... !!!
    [MCU2_0]      4.128383 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU2_0]      4.128412 s: SCICLIENT: DMSC FW revision 0x9
    [MCU2_0]      4.128431 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0]      4.128450 s: SCICLIENT: Init ... Done !!!
    [MCU2_0]      4.128467 s: UDMA: Init ... !!!
    [MCU2_0]      4.129331 s: UDMA: Init ... Done !!!
    [MCU2_0]      4.129359 s: UDMA: Init for CSITX/CSIRX ... !!!
    [MCU2_0]      4.129796 s: UDMA: Init for CSITX/CSIRX ... Done !!!
    [MCU2_0]      4.129824 s: MEM: Init ... !!!
    [MCU2_0]      4.129846 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bb000000 of size 8388608 bytes !!!
    [MCU2_0]      4.129887 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
    [MCU2_0]      4.129921 s: MEM: Init ... Done !!!
    [MCU2_0]      4.129938 s: IPC: Init ... !!!
    [MCU2_0]      4.129969 s: IPC: 11 CPUs participating in IPC !!!
    [MCU2_0]      4.129999 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0]      4.228237 s: set TCA9539 pin is output! *****
    [MCU2_0]      4.327599 s: **** appGMSL loop High !
    [MCU2_0]      4.428042 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      4.428503 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]      5.428035 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      5.428492 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]      6.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      6.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]      7.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      7.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]      8.428035 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      8.428489 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]      9.428035 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]      9.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     10.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     10.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     11.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     11.428491 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     12.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     12.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     13.428034 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     13.428490 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     13.987203 s: IPC: HLOS is ready !!!
    [MCU2_0]     13.994711 s: IPC: Init ... Done !!!
    [MCU2_0]     13.994754 s: APP: Syncing with 10 CPUs ... !!!
    [MCU2_0]     14.428049 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     14.428514 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     14.703835 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU2_0]     14.703862 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0]     14.704671 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0]     14.704709 s: ETHFW: Init ... !!!
    [MCU2_0]     14.810601 s: ETHFW: Warning: Using 6 random MAC address(es)
    [MCU2_0]     14.810640 s: ETHFW: Warning: Using 6 MAC address(es) from static pool
    [MCU2_0]     14.810768 s: ETHFW: CPSW recovery is not enabled
    [MCU2_0]     14.810821 s: ETHFW: Shared multicasts:
    [MCU2_0]     14.810854 s: ETHFW:   01:00:5e:00:00:01
    [MCU2_0]     14.810880 s: ETHFW:   01:00:5e:00:00:fb
    [MCU2_0]     14.810903 s: ETHFW:   01:00:5e:00:00:fc
    [MCU2_0]     14.810927 s: ETHFW:   33:33:00:00:00:01
    [MCU2_0]     14.810949 s: ETHFW:   33:33:ff:1d:92:c2
    [MCU2_0]     14.810972 s: ETHFW:   01:80:c2:00:00:00
    [MCU2_0]     14.810995 s: ETHFW:   01:80:c2:00:00:03
    [MCU2_0]     14.811015 s: ETHFW: Reserved multicasts:
    [MCU2_0]     14.811038 s: ETHFW:   01:80:c2:00:00:0e
    [MCU2_0]     14.811062 s: ETHFW:   01:1b:19:00:00:00
    [MCU2_0]     14.811179 s: EnetMcm: CPSW_9G on MAIN NAVSS
    [MCU2_0]     14.825840 s: ETHFW: 0 VLAN entries added in ALE table
    [MCU2_0]     14.826016 s:
    [MCU2_0] ETHFW Version   : 0.04.00
    [MCU2_0]     14.826044 s: ETHFW Build Date: Feb 28, 2024
    [MCU2_0]     14.826062 s: ETHFW Build Time: 20:24:20
    [MCU2_0]     14.826079 s: ETHFW Commit SHA: c65f39e2
    [MCU2_0]     14.826118 s: ETHFW: Init ... DONE !!!
    [MCU2_0]     14.826312 s: unibase-1.1.4-jacinto
    [MCU2_0]     14.826810 s: Starting lwIP, local interface IP is dhcp-enabled
    [MCU2_0]     14.832380 s: ETHFW: Host MAC address: 70:bf:56:60:e6:c2
    [MCU2_0]     14.833602 s: ETHFW: Enable gPTP on MAC port 3 (tilld3)
    [MCU2_0]     14.833638 s: ETHFW: Enable gPTP on MAC port 5 (tilld5)
    [MCU2_0]     14.833711 s: ETHFW: TimeSync PTP enabled
    [MCU2_0]     14.833735 s: ETHFW: Remove server Init ... !!!
    [MCU2_0]     14.833797 s: ETHFW: Virtual port configuration:
    [MCU2_0]     14.834257 s: ETHFW: CpswProxyServer: initialization completed (core: mcu2_0)
    [MCU2_0]     14.834292 s: ETHFW: Remove server Init ... DONE !!!
    [MCU2_0]     14.835131 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
    [MCU2_0]     14.835188 s: Added interface 'ti0', IP is 0.0.0.0
    [MCU2_0]     14.883610 s: FVID2: Init ... !!!
    [MCU2_0]     14.883675 s: FVID2: Init ... Done !!!
    [MCU2_0]     14.883699 s: SCICLIENT: Sciclient_pmSetModuleState module=275 state=2
    [MCU2_0]     14.883798 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.883831 s: DSS: Init ... !!!
    [MCU2_0]     14.883849 s: DSS: Display type is eDP !!!
    [MCU2_0]     14.883866 s: DSS: M2M Path is enabled !!!
    [MCU2_0]     14.883883 s: DSS: SoC init ... !!!
    [MCU2_0]     14.883898 s: SCICLIENT: Sciclient_pmSetModuleState module=218 state=0
    [MCU2_0]     14.884014 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884036 s: SCICLIENT: Sciclient_pmSetModuleState module=404 state=2
    [MCU2_0]     14.884095 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884118 s: SCICLIENT: Sciclient_pmSetModuleState module=217 state=2
    [MCU2_0]     14.884171 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884192 s: SCICLIENT: Sciclient_pmSetModuleState module=404 state=2
    [MCU2_0]     14.884245 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884264 s: SCICLIENT: Sciclient_pmSetModuleState module=217 state=2
    [MCU2_0]     14.884314 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884333 s: SCICLIENT: Sciclient_pmSetModuleState module=218 state=0
    [MCU2_0]     14.884382 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884403 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=218 clk=3 freq=148500000
    [MCU2_0]     14.884490 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
    [MCU2_0]     14.884511 s: SCICLIENT: Sciclient_pmModuleClkRequest module=218 clk=3 state=2 flag=2
    [MCU2_0]     14.884578 s: SCICLIENT: Sciclient_pmModuleClkRequest success
    [MCU2_0]     14.884644 s: SCICLIENT: Sciclient_pmSetModuleState module=218 state=2
    [MCU2_0]     14.884735 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.884759 s: DSS: SoC init ... Done !!!
    [MCU2_0]     14.884777 s: DSS: Board init ... !!!
    [MCU2_0]     14.884793 s: DSS: Board init ... Done !!!
    [MCU2_0]     14.903268 s: DSS: Init ... Done !!!
    [MCU2_0]     14.903311 s: VHWA: VPAC Init ... !!!
    [MCU2_0]     14.903330 s: SCICLIENT: Sciclient_pmSetModuleState module=399 state=2
    [MCU2_0]     14.903441 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.903467 s: VHWA: LDC Init ... !!!
    [MCU2_0]     14.905130 s: VHWA: LDC Init ... Done !!!
    [MCU2_0]     14.905168 s: VHWA: MSC Init ... !!!
    [MCU2_0]     14.911035 s: VHWA: MSC Init ... Done !!!
    [MCU2_0]     14.911075 s: VHWA: NF Init ... !!!
    [MCU2_0]     14.911936 s: VHWA: NF Init ... Done !!!
    [MCU2_0]     14.911969 s: VHWA: VISS Init ... !!!
    [MCU2_0]     14.917427 s: VHWA: VISS Init ... Done !!!
    [MCU2_0]     14.917470 s: VHWA: VPAC Init ... Done !!!
    [MCU2_0]     14.917501 s:  VX_ZONE_INIT:Enabled
    [MCU2_0]     14.917519 s:  VX_ZONE_ERROR:Enabled
    [MCU2_0]     14.917536 s:  VX_ZONE_WARNING:Enabled
    [MCU2_0]     14.918948 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0
    [MCU2_0]     14.919062 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF
    [MCU2_0]     14.919151 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1
    [MCU2_0]     14.919247 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1
    [MCU2_0]     14.919329 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2
    [MCU2_0]     14.919480 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1
    [MCU2_0]     14.919590 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1
    [MCU2_0]     14.919801 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2
    [MCU2_0]     14.919950 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1
    [MCU2_0]     14.920062 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2
    [MCU2_0]     14.920164 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX
    [MCU2_0]     14.920279 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3
    [MCU2_0]     14.920386 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4
    [MCU2_0]     14.920479 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5
    [MCU2_0]     14.920573 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6
    [MCU2_0]     14.920760 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7
    [MCU2_0]     14.920863 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8
    [MCU2_0]     14.920962 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1
    [MCU2_0]     14.921065 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2
    [MCU2_0]     14.921156 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3
    [MCU2_0]     14.921254 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4
    [MCU2_0]     14.921342 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX2
    [MCU2_0]     14.921478 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE9
    [MCU2_0]     14.921579 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE10
    [MCU2_0]     14.921763 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE11
    [MCU2_0]     14.921871 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE12
    [MCU2_0]     14.921911 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU2_0]     14.921935 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_0]     14.929356 s: APP: Register tivxRegisterTiovxPracticeTargetIpuKernels to CPU_mcu2_0 !!!
    [MCU2_0]     14.929458 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_0]     14.929481 s: CSI2RX: Init ... !!!
    [MCU2_0]     14.929496 s: SCICLIENT: Sciclient_pmSetModuleState module=189 state=2
    [MCU2_0]     14.929579 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.929660 s: SCICLIENT: Sciclient_pmSetModuleState module=72 state=2
    [MCU2_0]     14.929722 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.929745 s: SCICLIENT: Sciclient_pmSetModuleState module=73 state=2
    [MCU2_0]     14.929797 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.929818 s: SCICLIENT: Sciclient_pmSetModuleState module=74 state=2
    [MCU2_0]     14.929865 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.929886 s: SCICLIENT: Sciclient_pmSetModuleState module=212 state=2
    [MCU2_0]     14.929949 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.929970 s: SCICLIENT: Sciclient_pmSetModuleState module=213 state=2
    [MCU2_0]     14.930028 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930049 s: SCICLIENT: Sciclient_pmSetModuleState module=214 state=2
    [MCU2_0]     14.930103 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930305 s: CSI2RX: Init ... Done !!!
    [MCU2_0]     14.930329 s: CSI2TX: Init ... !!!
    [MCU2_0]     14.930345 s: SCICLIENT: Sciclient_pmSetModuleState module=189 state=2
    [MCU2_0]     14.930401 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930424 s: SCICLIENT: Sciclient_pmSetModuleState module=75 state=2
    [MCU2_0]     14.930471 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930492 s: SCICLIENT: Sciclient_pmSetModuleState module=76 state=2
    [MCU2_0]     14.930542 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930562 s: SCICLIENT: Sciclient_pmSetModuleState module=402 state=2
    [MCU2_0]     14.930652 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930677 s: SCICLIENT: Sciclient_pmSetModuleState module=403 state=2
    [MCU2_0]     14.930745 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_0]     14.930821 s: CSI2TX: Init ... Done !!!
    [MCU2_0]     14.930844 s: ISS: Init ... !!!
    [MCU2_0]     14.930869 s: IssSensor_Init ... Done !!!
    [MCU2_0]     14.930929 s: IttRemoteServer_Init ... Done !!!
    [MCU2_0]     14.930948 s: ISS: Init ... Done !!!
    [MCU2_0]     14.930967 s: VISS REMOTE SERVICE: Init ... !!!
    [MCU2_0]     14.931015 s: VISS REMOTE SERVICE: Init ... Done !!!
    [MCU2_0]     14.931037 s: UDMA Copy: Init ... !!!
    [MCU2_0]     14.931055 s: [MEM free rtos]: appMemAlloc Enter
    [MCU2_0]     14.931099 s: [MEM free rtos]: appMemAlloc Enter
    [MCU2_0]     14.931123 s: [MEM free rtos]: appMemAlloc Enter
    [MCU2_0]     14.931142 s: [MEM free rtos]: appMemAlloc Enter
    [MCU2_0]     14.931161 s: [MEM free rtos]: appMemAlloc Enter
    [MCU2_0]     14.932090 s: UDMA Copy: Init ... Done !!!
    [MCU2_0]     14.932160 s: APP: Init ... Done !!!
    [MCU2_0]     14.932182 s: APP: Run ... !!!
    [MCU2_0]     14.932199 s: IPC: Starting echo test ...
    [MCU2_0]     14.933437 s: APP: Run ... Done !!!
    [MCU2_0]     14.933466 s: ****** loop *****
    [MCU2_0]     14.934923 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[.] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935004 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[.] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935070 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[.] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935136 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935203 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935269 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935335 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.]
    [MCU2_0]     14.935400 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.]
    [MCU2_0]     14.935466 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU2_0]     15.255571 s: ETHFW: VIRT_PORT_INFO | C2S | core=0 endpt=1026
    [MCU2_0]     15.255659 s: ETHFW: VIRT_PORT_INFO | S2C | switchPortMask=1 macPortMask=10
    [MCU2_0]     15.255786 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=0
    [MCU2_0]     15.255954 s: ETHFW: ATTACH_EXT | S2C | token=0 rxMtu=1522 features=8 flow=114,0 rxPsil=0x4a00 txPsil=0xca00 macAddr=70:e9:9c:c4:71:83
    [MCU2_0]     15.256068 s: ETHFW: ATTACH_EXT | C2S | core=0 endpt=1026 virtPort=4
    [MCU2_0]     15.256165 s: ETHFW: ATTACH_EXT | S2C | token=400 rxMtu=1522 features=0 flow=114,1 rxPsil=0x4a00 txPsil=0xca01 macAddr=70:2b:0f:cc:25:61
    [MCU2_0]     15.428062 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     15.428542 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     15.825783 s: INF:cbase:cb_rawsock_open:dmaTxChId=-1 dmaRxChId=-1 nTxPkts=0 nRxPkts=0 pktSize=0
    [MCU2_0] INF:gptp:gptpnet_init:Open lldtsync OK!
    [MCU2_0] INF:gptp:000010-750168:domainIndex=0, GM changed old=00:00:00:00:00:00:00:00, new=70:BF:56:FF:FE:60:E6:C2
    [MCU2_0] INF:gptp:set_phase_offsetGM:domainNumber=0, New adjustment(New GM?)
    [MCU2_0]     15.932611 s: GPIO_read GPIO_TEST1 value:0
    [MCU2_0]     15.932651 s: GPIO_read GPIO_TEST2 value:0
    [MCU2_0]     15.932676 s: ****** loop *****
    [MCU2_0]     16.428062 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     16.428543 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     16.536729 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=400 macAdd=70:2b:0f:cc:25:61 flowIdx=114,1
    [MCU2_0]     16.539585 s: ETHFW: REGISTER_MAC | S2C | status=0
    [MCU2_0]     16.555357 s: ETHFW: REGISTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=70:e9:9c:c4:71:83 flowIdx=114,0
    [MCU2_0]     16.560924 s: Cpsw_ioctlInternal: Registered MAC address (ALE entry=9, policer entry=1)
    [MCU2_0]     16.560961 s:
    [MCU2_0]     16.567552 s: ETHFW: REGISTER_MAC | S2C | status=0
    [MCU2_0]     16.577653 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:00:00:00:01 vlanId=65535 flowIdx=114,0
    [MCU2_0]     16.580414 s: filterAddMacSharedCb: Address found: 33:33:0:0:0:1
    [MCU2_0]     16.585945 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     16.586079 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:00:5e:00:00:01 vlanId=65535 flowIdx=114,0
    [MCU2_0]     16.588877 s: filterAddMacSharedCb: Address found: 1:0:5e:0:0:1
    [MCU2_0]     16.594400 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     16.597346 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=33:33:ff:c4:71:83 vlanId=65535 flowIdx=114,0
    [MCU2_0]     16.602941 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     16.635258 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:00 vlanId=65535 flowIdx=114,0
    [MCU2_0]     16.638095 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:0
    [MCU2_0]     16.643678 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     16.643822 s: ETHFW: ADD_FILTER_MAC | C2S | core=0 endpt=1026 token=0 macAdd=01:80:c2:00:00:03 vlanId=65535 flowIdx=114,0
    [MCU2_0]     16.646595 s: filterAddMacSharedCb: Address found: 1:80:c2:0:0:3
    [MCU2_0]     16.652167 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     16.652299 s: ETHFW: ADD_FILTER_MAC | S2C | status=0
    [MCU2_0]     43.428055 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     43.428535 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     43.932610 s: GPIO_read GPIO_TEST1 value:1
    [MCU2_0]     43.932651 s: GPIO_read GPIO_TEST2 value:0
    [MCU2_0]     43.932675 s: ****** loop *****
    [MCU2_1]      4.139392 s: CIO: Init ... Done !!!
    [MCU2_1]      4.139445 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_1]      4.139470 s: CPU is running FreeRTOS
    [MCU2_1]      4.139485 s: APP: Init ... !!!
    [MCU2_1]      4.139517 s: SCICLIENT: Init ... !!!
    [MCU2_1]      4.139638 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU2_1]      4.139668 s: SCICLIENT: DMSC FW revision 0x9
    [MCU2_1]      4.139688 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_1]      4.139707 s: SCICLIENT: Init ... Done !!!
    [MCU2_1]      4.139724 s: UDMA: Init ... !!!
    [MCU2_1]      4.140578 s: UDMA: Init ... Done !!!
    [MCU2_1]      4.140610 s: MEM: Init ... !!!
    [MCU2_1]      4.140634 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bb800000 of size 8388608 bytes !!!
    [MCU2_1]      4.140675 s: MEM: Init ... Done !!!
    [MCU2_1]      4.140691 s: IPC: Init ... !!!
    [MCU2_1]      4.140725 s: IPC: 11 CPUs participating in IPC !!!
    [MCU2_1]      4.140756 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_1]     14.004137 s: IPC: HLOS is ready !!!
    [MCU2_1]     14.011166 s: IPC: Init ... Done !!!
    [MCU2_1]     14.011206 s: APP: Syncing with 10 CPUs ... !!!
    [MCU2_1]     14.703835 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU2_1]     14.703864 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_1]     14.704657 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_1]     14.704696 s: FVID2: Init ... !!!
    [MCU2_1]     14.704740 s: FVID2: Init ... Done !!!
    [MCU2_1]     14.704759 s: VHWA: DMPAC: Init ... !!!
    [MCU2_1]     14.704777 s: SCICLIENT: Sciclient_pmSetModuleState module=92 state=2
    [MCU2_1]     14.704897 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]     14.704921 s: SCICLIENT: Sciclient_pmSetModuleState module=96 state=2
    [MCU2_1]     14.705041 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU2_1]     14.705062 s: VHWA: DOF Init ... !!!
    [MCU2_1]     14.711233 s: VHWA: DOF Init ... Done !!!
    [MCU2_1]     14.711273 s: VHWA: SDE Init ... !!!
    [MCU2_1]     14.713250 s: VHWA: SDE Init ... Done !!!
    [MCU2_1]     14.713281 s: VHWA: DMPAC: Init ... Done !!!
    [MCU2_1]     14.713310 s:  VX_ZONE_INIT:Enabled
    [MCU2_1]     14.713329 s:  VX_ZONE_ERROR:Enabled
    [MCU2_1]     14.713346 s:  VX_ZONE_WARNING:Enabled
    [MCU2_1]     14.714678 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1
    [MCU2_1]     14.714778 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE
    [MCU2_1]     14.714868 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF
    [MCU2_1]     14.714902 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU2_1]     14.714926 s: APP: OpenVX Target kernel init ... !!!
    [MCU2_1]     14.715067 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU2_1]     14.715096 s: APP: Init ... Done !!!
    [MCU2_1]     14.715114 s: APP: Run ... !!!
    [MCU2_1]     14.715129 s: IPC: Starting echo test ...
    [MCU2_1]     14.716276 s: APP: Run ... Done !!!
    [MCU2_1]     14.717223 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_1]     14.717311 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_1]     14.717381 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_1]     14.717450 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU2_1]     14.717518 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.]
    [MCU2_1]     14.717585 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.]
    [MCU2_1]     14.717652 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU2_1]     14.734198 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU2_1]     14.934547 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_0]      4.183618 s: CIO: Init ... Done !!!
    [MCU3_0]      4.183672 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_0]      4.183697 s: CPU is running FreeRTOS
    [MCU3_0]      4.183712 s: APP: Init ... !!!
    [MCU3_0]      4.183739 s: SCICLIENT: Init ... !!!
    [MCU3_0]      4.183857 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU3_0]      4.183885 s: SCICLIENT: DMSC FW revision 0x9
    [MCU3_0]      4.183905 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU3_0]      4.183924 s: SCICLIENT: Init ... Done !!!
    [MCU3_0]      4.183942 s: MEM: Init ... !!!
    [MCU3_0]      4.183964 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc000000 of size 8388608 bytes !!!
    [MCU3_0]      4.184004 s: MEM: Init ... Done !!!
    [MCU3_0]      4.184020 s: IPC: Init ... !!!
    [MCU3_0]      4.184051 s: IPC: 11 CPUs participating in IPC !!!
    [MCU3_0]      4.184082 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU3_0]     14.142526 s: IPC: HLOS is ready !!!
    [MCU3_0]     14.149576 s: IPC: Init ... Done !!!
    [MCU3_0]     14.149617 s: APP: Syncing with 10 CPUs ... !!!
    [MCU3_0]     14.703833 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU3_0]     14.703858 s: REMOTE_SERVICE: Init ... !!!
    [MCU3_0]     14.704669 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU3_0]     14.704722 s:  VX_ZONE_INIT:Enabled
    [MCU3_0]     14.704741 s:  VX_ZONE_ERROR:Enabled
    [MCU3_0]     14.704758 s:  VX_ZONE_WARNING:Enabled
    [MCU3_0]     14.706022 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-0
    [MCU3_0]     14.706067 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU3_0]     14.706092 s: APP: OpenVX Target kernel init ... !!!
    [MCU3_0]     14.706111 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU3_0]     14.706131 s: APP: Init ... Done !!!
    [MCU3_0]     14.706148 s: APP: Run ... !!!
    [MCU3_0]     14.706163 s: IPC: Starting echo test ...
    [MCU3_0]     14.707322 s: APP: Run ... Done !!!
    [MCU3_0]     14.707858 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[.] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_0]     14.708176 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_0]     14.708247 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_0]     14.708957 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[.]
    [MCU3_0]     14.709147 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[P]
    [MCU3_0]     14.709626 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_0]     14.716700 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_0]     14.734155 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[s] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_0]     14.934565 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[s] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_1]      4.228528 s: CIO: Init ... Done !!!
    [MCU3_1]      4.228584 s: ### CPU Frequency = 1000000000 Hz
    [MCU3_1]      4.228608 s: CPU is running FreeRTOS
    [MCU3_1]      4.228625 s: APP: Init ... !!!
    [MCU3_1]      4.228653 s: SCICLIENT: Init ... !!!
    [MCU3_1]      4.228772 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU3_1]      4.228801 s: SCICLIENT: DMSC FW revision 0x9
    [MCU3_1]      4.228820 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU3_1]      4.228840 s: SCICLIENT: Init ... Done !!!
    [MCU3_1]      4.228857 s: MEM: Init ... !!!
    [MCU3_1]      4.228880 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bc800000 of size 8388608 bytes !!!
    [MCU3_1]      4.228918 s: MEM: Init ... Done !!!
    [MCU3_1]      4.228934 s: IPC: Init ... !!!
    [MCU3_1]      4.228965 s: IPC: 11 CPUs participating in IPC !!!
    [MCU3_1]      4.228995 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU3_1]     14.535030 s: IPC: HLOS is ready !!!
    [MCU3_1]     14.541750 s: IPC: Init ... Done !!!
    [MCU3_1]     14.541785 s: APP: Syncing with 10 CPUs ... !!!
    [MCU3_1]     14.703834 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU3_1]     14.703860 s: REMOTE_SERVICE: Init ... !!!
    [MCU3_1]     14.704680 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU3_1]     14.704728 s:  VX_ZONE_INIT:Enabled
    [MCU3_1]     14.704746 s:  VX_ZONE_ERROR:Enabled
    [MCU3_1]     14.704763 s:  VX_ZONE_WARNING:Enabled
    [MCU3_1]     14.706033 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU3-1
    [MCU3_1]     14.706077 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU3_1]     14.706103 s: APP: OpenVX Target kernel init ... !!!
    [MCU3_1]     14.706123 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU3_1]     14.706143 s: APP: Init ... Done !!!
    [MCU3_1]     14.706160 s: APP: Run ... !!!
    [MCU3_1]     14.706175 s: IPC: Starting echo test ...
    [MCU3_1]     14.707358 s: APP: Run ... Done !!!
    [MCU3_1]     14.707867 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[s] mcu4_0[x] mcu4_1[x] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_1]     14.708184 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_1]     14.708256 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU3_1]     14.708963 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[.]
    [MCU3_1]     14.709186 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[P]
    [MCU3_1]     14.709633 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_1]     14.716721 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_1]     14.734175 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[s] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU3_1]     14.934574 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[s] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_0]      4.299088 s: CIO: Init ... Done !!!
    [MCU4_0]      4.299144 s: ### CPU Frequency = 1000000000 Hz
    [MCU4_0]      4.299170 s: CPU is running FreeRTOS
    [MCU4_0]      4.299187 s: APP: Init ... !!!
    [MCU4_0]      4.299219 s: SCICLIENT: Init ... !!!
    [MCU4_0]      4.299345 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU4_0]      4.299377 s: SCICLIENT: DMSC FW revision 0x9
    [MCU4_0]      4.299398 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU4_0]      4.299418 s: SCICLIENT: Init ... Done !!!
    [MCU4_0]      4.299436 s: UDMA: Init ... !!!
    [MCU4_0]      4.300300 s: UDMA: Init ... Done !!!
    [MCU4_0]      4.300331 s: MEM: Init ... !!!
    [MCU4_0]      4.300359 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bd000000 of size 8388608 bytes !!!
    [MCU4_0]      4.300405 s: MEM: Init ... Done !!!
    [MCU4_0]      4.300421 s: IPC: Init ... !!!
    [MCU4_0]      4.300455 s: IPC: 11 CPUs participating in IPC !!!
    [MCU4_0]      4.300485 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU4_0]     14.621071 s: IPC: HLOS is ready !!!
    [MCU4_0]     14.627554 s: IPC: Init ... Done !!!
    [MCU4_0]     14.627595 s: APP: Syncing with 10 CPUs ... !!!
    [MCU4_0]     14.703836 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU4_0]     14.703863 s: REMOTE_SERVICE: Init ... !!!
    [MCU4_0]     14.704697 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU4_0]     14.704735 s: FVID2: Init ... !!!
    [MCU4_0]     14.704774 s: FVID2: Init ... Done !!!
    [MCU4_0]     14.704792 s: VHWA: VPAC Init ... !!!
    [MCU4_0]     14.704810 s: SCICLIENT: Sciclient_pmSetModuleState module=400 state=2
    [MCU4_0]     14.704985 s: SCICLIENT: Sciclient_pmSetModuleState success
    [MCU4_0]     14.705010 s: VHWA: LDC Init ... !!!
    [MCU4_0]     14.709124 s: VHWA: LDC Init ... Done !!!
    [MCU4_0]     14.709194 s: VHWA: MSC Init ... !!!
    [MCU4_0]     14.716398 s: VHWA: MSC Init ... Done !!!
    [MCU4_0]     14.716477 s: VHWA: NF Init ... !!!
    [MCU4_0]     14.717316 s: VHWA: NF Init ... Done !!!
    [MCU4_0]     14.717350 s: VHWA: VISS Init ... !!!
    [MCU4_0]     14.722693 s: VHWA: VISS Init ... Done !!!
    [MCU4_0]     14.722731 s: VHWA: VPAC Init ... Done !!!
    [MCU4_0]     14.722765 s:  VX_ZONE_INIT:Enabled
    [MCU4_0]     14.722783 s:  VX_ZONE_ERROR:Enabled
    [MCU4_0]     14.722800 s:  VX_ZONE_WARNING:Enabled
    [MCU4_0]     14.724038 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU4-0
    [MCU4_0]     14.724134 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_NF
    [MCU4_0]     14.724219 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_LDC1
    [MCU4_0]     14.724303 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_MSC1
    [MCU4_0]     14.724399 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_MSC2
    [MCU4_0]     14.724525 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC2_VISS1
    [MCU4_0]     14.724560 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU4_0]     14.724583 s: APP: OpenVX Target kernel init ... !!!
    [MCU4_0]     14.731334 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU4_0]     14.731365 s: VISS REMOTE SERVICE: Init ... !!!
    [MCU4_0]     14.731414 s: VISS REMOTE SERVICE: Init ... Done !!!
    [MCU4_0]     14.731437 s: UDMA Copy: Init ... !!!
    [MCU4_0]     14.731453 s: [MEM free rtos]: appMemAlloc Enter
    [MCU4_0]     14.731489 s: [MEM free rtos]: appMemAlloc Enter
    [MCU4_0]     14.731509 s: [MEM free rtos]: appMemAlloc Enter
    [MCU4_0]     14.731527 s: [MEM free rtos]: appMemAlloc Enter
    [MCU4_0]     14.731546 s: [MEM free rtos]: appMemAlloc Enter
    [MCU4_0]     14.732429 s: UDMA Copy: Init ... Done !!!
    [MCU4_0]     14.732464 s: APP: Init ... Done !!!
    [MCU4_0]     14.732486 s: APP: Run ... !!!
    [MCU4_0]     14.732503 s: IPC: Starting echo test ...
    [MCU4_0]     14.733651 s: APP: Run ... Done !!!
    [MCU4_0]     14.734854 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[.] mcu3_1[.] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.734936 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[.] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.735008 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[.] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.735075 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[.] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.735142 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[.] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.735207 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[.] c7x_4[.]
    [MCU4_0]     14.735270 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[.]
    [MCU4_0]     14.735337 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_0]     14.934582 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[s] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_1]      4.333077 s: CIO: Init ... Done !!!
    [MCU4_1]      4.333137 s: ### CPU Frequency = 1000000000 Hz
    [MCU4_1]      4.333160 s: CPU is running FreeRTOS
    [MCU4_1]      4.333177 s: APP: Init ... !!!
    [MCU4_1]      4.333204 s: SCICLIENT: Init ... !!!
    [MCU4_1]      4.333324 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [MCU4_1]      4.333352 s: SCICLIENT: DMSC FW revision 0x9
    [MCU4_1]      4.333372 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU4_1]      4.333392 s: SCICLIENT: Init ... Done !!!
    [MCU4_1]      4.333409 s: MEM: Init ... !!!
    [MCU4_1]      4.333431 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ bd800000 of size 8388608 bytes !!!
    [MCU4_1]      4.333472 s: MEM: Init ... Done !!!
    [MCU4_1]      4.333489 s: IPC: Init ... !!!
    [MCU4_1]      4.333522 s: IPC: 11 CPUs participating in IPC !!!
    [MCU4_1]      4.333554 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU4_1]     14.697108 s: IPC: HLOS is ready !!!
    [MCU4_1]     14.703766 s: IPC: Init ... Done !!!
    [MCU4_1]     14.703804 s: APP: Syncing with 10 CPUs ... !!!
    [MCU4_1]     14.703834 s: APP: Syncing with 10 CPUs ... Done !!!
    [MCU4_1]     14.703857 s: REMOTE_SERVICE: Init ... !!!
    [MCU4_1]     14.704700 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU4_1]     14.704749 s:  VX_ZONE_INIT:Enabled
    [MCU4_1]     14.704769 s:  VX_ZONE_ERROR:Enabled
    [MCU4_1]     14.704785 s:  VX_ZONE_WARNING:Enabled
    [MCU4_1]     14.706074 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU4-1
    [MCU4_1]     14.706112 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [MCU4_1]     14.706135 s: APP: OpenVX Target kernel init ... !!!
    [MCU4_1]     14.706154 s: APP: OpenVX Target kernel init ... Done !!!
    [MCU4_1]     14.706174 s: APP: Init ... Done !!!
    [MCU4_1]     14.706191 s: APP: Run ... !!!
    [MCU4_1]     14.706206 s: IPC: Starting echo test ...
    [MCU4_1]     14.707389 s: APP: Run ... Done !!!
    [MCU4_1]     14.707883 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU4_1]     14.708192 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU4_1]     14.708264 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[x] c7x_3[x] c7x_4[x]
    [MCU4_1]     14.708989 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[.]
    [MCU4_1]     14.709089 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[P]
    [MCU4_1]     14.709605 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_1]     14.716731 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_1]     14.734187 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [MCU4_1]     14.934593 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[s] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[P]
    [C7x_1 ]      4.696247 s: CIO: Init ... Done !!!
    [C7x_1 ]      4.696263 s: ### CPU Frequency = 1000000000 Hz
    [C7x_1 ]      4.696274 s: CPU is running FreeRTOS
    [C7x_1 ]      4.696283 s: APP: Init ... !!!
    [C7x_1 ]      4.696291 s: SCICLIENT: Init ... !!!
    [C7x_1 ]      4.696400 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_1 ]      4.696413 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_1 ]      4.696424 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_1 ]      4.696435 s: SCICLIENT: Init ... Done !!!
    [C7x_1 ]      4.696445 s: UDMA: Init ... !!!
    [C7x_1 ]      4.697276 s: UDMA: Init ... Done !!!
    [C7x_1 ]      4.697288 s: MEM: Init ... !!!
    [C7x_1 ]      4.697298 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_1 ]      4.697320 s: MEM: Init ... Done !!!
    [C7x_1 ]      4.697329 s: IPC: Init ... !!!
    [C7x_1 ]      4.697343 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_1 ]      4.697358 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_1 ]     13.753297 s: IPC: HLOS is ready !!!
    [C7x_1 ]     13.757894 s: IPC: Init ... Done !!!
    [C7x_1 ]     13.757909 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_1 ]     14.703837 s: APP: Syncing with 10 CPUs ... Done !!!
    [C7x_1 ]     14.703855 s: REMOTE_SERVICE: Init ... !!!
    [C7x_1 ]     14.704075 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_1 ]     14.704123 s:  VX_ZONE_INIT:Enabled
    [C7x_1 ]     14.704137 s:  VX_ZONE_ERROR:Enabled
    [C7x_1 ]     14.704147 s:  VX_ZONE_WARNING:Enabled
    [C7x_1 ]     14.704571 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1
    [C7x_1 ]     14.704639 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2
    [C7x_1 ]     14.704709 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3
    [C7x_1 ]     14.704771 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4
    [C7x_1 ]     14.704833 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5
    [C7x_1 ]     14.704898 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6
    [C7x_1 ]     14.704964 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7
    [C7x_1 ]     14.705032 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8
    [C7x_1 ]     14.705056 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [C7x_1 ]     14.705069 s: APP: OpenVX Target kernel init ... !!!
    [C7x_1 ]     14.705765 s: APP: Register C7120 !!!
    [C7x_1 ]     14.705790 s: APP: Register tivxRegisterTiovxPracticeTargetC7XKernels to CPU_c7x_1!!!
    [C7x_1 ]     14.705815 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_1 ]     14.705826 s: APP: Init ... Done !!!
    [C7x_1 ]     14.705835 s: APP: Run ... !!!
    [C7x_1 ]     14.705845 s: IPC: Starting echo test ...
    [C7x_1 ]     14.706113 s: APP: Run ... Done !!!
    [C7x_1 ]     14.708091 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[s] c7x_2[x] c7x_3[x] c7x_4[x]
    [C7x_1 ]     14.708139 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[s] c7x_2[x] c7x_3[x] c7x_4[x]
    [C7x_1 ]     14.708186 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[x] c7x_3[x] c7x_4[x]
    [C7x_1 ]     14.709007 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[x] c7x_3[P] c7x_4[.]
    [C7x_1 ]     14.709069 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[x] c7x_3[P] c7x_4[P]
    [C7x_1 ]     14.709590 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P]
    [C7x_1 ]     14.716740 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P]
    [C7x_1 ]     14.734210 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P]
    [C7x_1 ]     14.934604 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[s] c7x_2[P] c7x_3[P] c7x_4[P]
    [C7x_2 ]      5.025053 s: CIO: Init ... Done !!!
    [C7x_2 ]      5.025068 s: ### CPU Frequency = 1000000000 Hz
    [C7x_2 ]      5.025080 s: CPU is running FreeRTOS
    [C7x_2 ]      5.025088 s: APP: Init ... !!!
    [C7x_2 ]      5.025096 s: SCICLIENT: Init ... !!!
    [C7x_2 ]      5.025205 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_2 ]      5.025218 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_2 ]      5.025228 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_2 ]      5.025240 s: SCICLIENT: Init ... Done !!!
    [C7x_2 ]      5.025249 s: UDMA: Init ... !!!
    [C7x_2 ]      5.026075 s: UDMA: Init ... Done !!!
    [C7x_2 ]      5.026086 s: MEM: Init ... !!!
    [C7x_2 ]      5.026097 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_2 ]      5.026118 s: MEM: Init ... Done !!!
    [C7x_2 ]      5.026127 s: IPC: Init ... !!!
    [C7x_2 ]      5.026141 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_2 ]      5.026156 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_2 ]     13.875857 s: IPC: HLOS is ready !!!
    [C7x_2 ]     13.880126 s: IPC: Init ... Done !!!
    [C7x_2 ]     13.880140 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_2 ]     14.703836 s: APP: Syncing with 10 CPUs ... Done !!!
    [C7x_2 ]     14.703852 s: REMOTE_SERVICE: Init ... !!!
    [C7x_2 ]     14.704073 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_2 ]     14.704097 s:  VX_ZONE_INIT:Enabled
    [C7x_2 ]     14.704132 s:  VX_ZONE_ERROR:Enabled
    [C7x_2 ]     14.704143 s:  VX_ZONE_WARNING:Enabled
    [C7x_2 ]     14.704954 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2
    [C7x_2 ]     14.705041 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_2
    [C7x_2 ]     14.705112 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_3
    [C7x_2 ]     14.705176 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_4
    [C7x_2 ]     14.705242 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_5
    [C7x_2 ]     14.705304 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_6
    [C7x_2 ]     14.705364 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_7
    [C7x_2 ]     14.705426 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-2_PRI_8
    [C7x_2 ]     14.705449 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [C7x_2 ]     14.705467 s: APP: OpenVX Target kernel init ... !!!
    [C7x_2 ]     14.706260 s: APP: Register C7120 !!!
    [C7x_2 ]     14.706698 s: APP: Register tivxRegisterTiovxPracticeTargetC7XKernels to CPU_c7x_2 !!!
    [C7x_2 ]     14.706735 s: Add Target Kernel Tiovxpractice fail! self_cpu(0) not match!
    [C7x_2 ]     14.706749 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_2 ]     14.706760 s: UDMA Copy: Init ... !!!
    [C7x_2 ]     14.706770 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_2 ]     14.706799 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_2 ]     14.706811 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_2 ]     14.706821 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_2 ]     14.706832 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_2 ]     14.708781 s: UDMA Copy: Init ... Done !!!
    [C7x_2 ]     14.708796 s: APP: Init ... Done !!!
    [C7x_2 ]     14.708805 s: APP: Run ... !!!
    [C7x_2 ]     14.708814 s: IPC: Starting echo test ...
    [C7x_2 ]     14.709071 s: APP: Run ... Done !!!
    [C7x_2 ]     14.709745 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[P] c7x_1[.] c7x_2[s] c7x_3[.] c7x_4[.]
    [C7x_2 ]     14.709793 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[.] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[.] c7x_4[.]
    [C7x_2 ]     14.709835 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[.] c7x_4[.]
    [C7x_2 ]     14.709878 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[.] c7x_4[.]
    [C7x_2 ]     14.709919 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[.]
    [C7x_2 ]     14.709961 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P]
    [C7x_2 ]     14.716748 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P]
    [C7x_2 ]     14.734218 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P]
    [C7x_2 ]     14.934614 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[s] c7x_3[P] c7x_4[P]
    [C7x_3 ]      5.340688 s: CIO: Init ... Done !!!
    [C7x_3 ]      5.340703 s: ### CPU Frequency = 1000000000 Hz
    [C7x_3 ]      5.340714 s: CPU is running FreeRTOS
    [C7x_3 ]      5.340723 s: APP: Init ... !!!
    [C7x_3 ]      5.340730 s: SCICLIENT: Init ... !!!
    [C7x_3 ]      5.340839 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_3 ]      5.340852 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_3 ]      5.340862 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_3 ]      5.340873 s: SCICLIENT: Init ... Done !!!
    [C7x_3 ]      5.340882 s: UDMA: Init ... !!!
    [C7x_3 ]      5.341717 s: UDMA: Init ... Done !!!
    [C7x_3 ]      5.341729 s: MEM: Init ... !!!
    [C7x_3 ]      5.341740 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_3 ]      5.341761 s: MEM: Init ... Done !!!
    [C7x_3 ]      5.341770 s: IPC: Init ... !!!
    [C7x_3 ]      5.341783 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_3 ]      5.341799 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_3 ]     13.991337 s: IPC: HLOS is ready !!!
    [C7x_3 ]     13.995851 s: IPC: Init ... Done !!!
    [C7x_3 ]     13.995869 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_3 ]     14.703837 s: APP: Syncing with 10 CPUs ... Done !!!
    [C7x_3 ]     14.703856 s: REMOTE_SERVICE: Init ... !!!
    [C7x_3 ]     14.704101 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_3 ]     14.704153 s:  VX_ZONE_INIT:Enabled
    [C7x_3 ]     14.704218 s:  VX_ZONE_ERROR:Enabled
    [C7x_3 ]     14.704253 s:  VX_ZONE_WARNING:Enabled
    [C7x_3 ]     14.704632 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3
    [C7x_3 ]     14.704717 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_2
    [C7x_3 ]     14.704788 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_3
    [C7x_3 ]     14.704864 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_4
    [C7x_3 ]     14.704937 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_5
    [C7x_3 ]     14.705011 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_6
    [C7x_3 ]     14.705085 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_7
    [C7x_3 ]     14.705157 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-3_PRI_8
    [C7x_3 ]     14.705183 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [C7x_3 ]     14.705196 s: APP: OpenVX Target kernel init ... !!!
    [C7x_3 ]     14.705899 s: APP: Register C7120 !!!
    [C7x_3 ]     14.705916 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_3 ]     14.705927 s: UDMA Copy: Init ... !!!
    [C7x_3 ]     14.705938 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_3 ]     14.705968 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_3 ]     14.705983 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_3 ]     14.705995 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_3 ]     14.706006 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_3 ]     14.708166 s: UDMA Copy: Init ... Done !!!
    [C7x_3 ]     14.708181 s: APP: Init ... Done !!!
    [C7x_3 ]     14.708190 s: APP: Run ... !!!
    [C7x_3 ]     14.708199 s: IPC: Starting echo test ...
    [C7x_3 ]     14.708441 s: APP: Run ... Done !!!
    [C7x_3 ]     14.709143 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[.] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[x] c7x_3[s] c7x_4[.]
    [C7x_3 ]     14.709274 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[x] c7x_3[s] c7x_4[.]
    [C7x_3 ]     14.709319 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[x] c7x_3[s] c7x_4[.]
    [C7x_3 ]     14.709362 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[x] c7x_3[s] c7x_4[P]
    [C7x_3 ]     14.709404 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[s] c7x_4[P]
    [C7x_3 ]     14.709646 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P]
    [C7x_3 ]     14.716758 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P]
    [C7x_3 ]     14.734231 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P]
    [C7x_3 ]     14.934626 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[s] c7x_4[P]
    [C7x_4 ]      5.655813 s: CIO: Init ... Done !!!
    [C7x_4 ]      5.655829 s: ### CPU Frequency = 1000000000 Hz
    [C7x_4 ]      5.655840 s: CPU is running FreeRTOS
    [C7x_4 ]      5.655848 s: APP: Init ... !!!
    [C7x_4 ]      5.655856 s: SCICLIENT: Init ... !!!
    [C7x_4 ]      5.655971 s: SCICLIENT: DMSC FW version [9.1.2--v09.01.02 (Kool Koala)]
    [C7x_4 ]      5.655985 s: SCICLIENT: DMSC FW revision 0x9
    [C7x_4 ]      5.655995 s: SCICLIENT: DMSC FW ABI revision 3.1
    [C7x_4 ]      5.656006 s: SCICLIENT: Init ... Done !!!
    [C7x_4 ]      5.656016 s: UDMA: Init ... !!!
    [C7x_4 ]      5.656853 s: UDMA: Init ... Done !!!
    [C7x_4 ]      5.656865 s: MEM: Init ... !!!
    [C7x_4 ]      5.656877 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 102000000 of size 33554432 bytes !!!
    [C7x_4 ]      5.656898 s: MEM: Init ... Done !!!
    [C7x_4 ]      5.656907 s: IPC: Init ... !!!
    [C7x_4 ]      5.656920 s: IPC: 11 CPUs participating in IPC !!!
    [C7x_4 ]      5.656935 s: IPC: Waiting for HLOS to be ready ... !!!
    [C7x_4 ]     14.136940 s: IPC: HLOS is ready !!!
    [C7x_4 ]     14.140815 s: IPC: Init ... Done !!!
    [C7x_4 ]     14.140832 s: APP: Syncing with 10 CPUs ... !!!
    [C7x_4 ]     14.703837 s: APP: Syncing with 10 CPUs ... Done !!!
    [C7x_4 ]     14.703856 s: REMOTE_SERVICE: Init ... !!!
    [C7x_4 ]     14.704135 s: REMOTE_SERVICE: Init ... Done !!!
    [C7x_4 ]     14.704160 s:  VX_ZONE_INIT:Enabled
    [C7x_4 ]     14.704232 s:  VX_ZONE_ERROR:Enabled
    [C7x_4 ]     14.704279 s:  VX_ZONE_WARNING:Enabled
    [C7x_4 ]     14.704628 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4
    [C7x_4 ]     14.704705 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_2
    [C7x_4 ]     14.704785 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_3
    [C7x_4 ]     14.704867 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_4
    [C7x_4 ]     14.704945 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_5
    [C7x_4 ]     14.705021 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_6
    [C7x_4 ]     14.705094 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_7
    [C7x_4 ]     14.705165 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-4_PRI_8
    [C7x_4 ]     14.705188 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
    [C7x_4 ]     14.705201 s: APP: OpenVX Target kernel init ... !!!
    [C7x_4 ]     14.705903 s: APP: Register C7120 !!!
    [C7x_4 ]     14.705919 s: APP: OpenVX Target kernel init ... Done !!!
    [C7x_4 ]     14.705930 s: UDMA Copy: Init ... !!!
    [C7x_4 ]     14.705940 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_4 ]     14.705974 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_4 ]     14.705989 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_4 ]     14.706000 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_4 ]     14.706011 s: [MEM free rtos]: appMemAlloc Enter
    [C7x_4 ]     14.708224 s: UDMA Copy: Init ... Done !!!
    [C7x_4 ]     14.708240 s: APP: Init ... Done !!!
    [C7x_4 ]     14.708250 s: APP: Run ... !!!
    [C7x_4 ]     14.708259 s: IPC: Starting echo test ...
    [C7x_4 ]     14.708504 s: APP: Run ... Done !!!
    [C7x_4 ]     14.709240 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[x] c7x_3[.] c7x_4[s]
    [C7x_4 ]     14.709293 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[.] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[x] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.709337 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[.] c7x_2[x] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.709380 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[.] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.709421 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[x] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.709640 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.716765 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[x] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.734240 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s]
    [C7x_4 ]     14.934630 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] mcu3_0[P] mcu3_1[P] mcu4_0[P] mcu4_1[P] c7x_1[P] c7x_2[P] c7x_3[P] c7x_4[s]
    [MCU2_0]     44.428059 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     44.428540 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     44.932612 s: GPIO_read GPIO_TEST1 value:0
    [MCU2_0]     44.932652 s: GPIO_read GPIO_TEST2 value:1
    [MCU2_0]     44.932677 s: ****** loop *****
    [MCU2_0]     45.428060 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     45.428540 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     45.932610 s: GPIO_read GPIO_TEST1 value:1
    [MCU2_0]     45.932650 s: GPIO_read GPIO_TEST2 value:0
    [MCU2_0]     45.932675 s: ****** loop *****
    [MCU2_0]     46.428057 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     46.428537 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     46.932611 s: GPIO_read GPIO_TEST1 value:0
    [MCU2_0]     46.932652 s: GPIO_read GPIO_TEST2 value:1
    [MCU2_0]     46.932677 s: ****** loop *****
    [MCU2_0]     47.428058 s: **** read TCA9539_0, 0x2 val:0xf8
    [MCU2_0]     47.428539 s: **** read TCA9539_1, 0x2 val:0x03
    [MCU2_0]     47.932616 s: GPIO_read GPIO_TEST1 value:1
    [MCU2_0]     47.932660 s: GPIO_read GPIO_TEST2 value:0
    [MCU2_0]     47.932686 s: ****** loop *****
    [MCU2_0]     48.428060 s: **** read TCA9539_0, 0x2 val:0xf8
    

    Note: Once you have modified the DDR configuration script, as long as it is executed using python3, the modifications are then generated, along with the.dtsi device tree file in the Linux sdk.

    However, in the first modification, I did not copy the .dtsi device tree file into the linux sdk, and the R5 core was running normally (MCU2_0 reaches the "App Run.. Done" log), I then copied the generated.dtsi file into the linux sdk and compiled it.

    After running the system again, the situation is the same as before.

    This means that whether or not I copy the.dtsi file into the linux sdk has no effect on the running of the R5 core. This does not seem reasonable.

  • Hi,

    So to summerize the issue here, with your configuration (i.e. considering 8GB DDR), with mcu2_0_ddr_local_heap_size = 8*MB; everything works fine and with mcu2_0_ddr_local_heap_size = 128*MB; you see the error "appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()"

    Am I correct here? If yes, I shall take your configuration at my end and test the same if I see this error. 

    This means that whether or not I copy the.dtsi file into the linux sdk has no effect on the running of the R5 core. This does not seem reasonable.

    This shouldn't be the case, once you build the vision_apps.dtbo from the generated dtsi, and copy it to the SD Card, you should see the issue again.

    Regards,

    Nikhil

  • Yes, you can try to change to 128MB and test

    I accidentally clicked on Resolved and it didn't give me a chance to double confirm...

  • Sure, no worries. Let me try this test at my end and get back to you by tomorrow.

    Regards,

    Nikhil

  • Okay, thank you.

    If there are no problems in your test, can you share your changes and test steps with me?

    I can check to see if I missed anything.

  • Sure.. will do that.

  • Hi,

    I'm able to reproduce this issue at my end. 

    If I increase the value of mcu2_0_ddr_local_heap_size to any value above 8MB, i'm getting "appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()" and hang in all the R5 cores.

    Let me deep dive to find the root cause of the same.

    I shall get back to you by tomorrow or early next week.

    Regards,

    Nikhil

  • Hi,

    Good news. 

    I found the root cause of this issue.

    The cause for the hang is because of this statement APP_ASSERT_SUCCESS().. This will put it in a while loop in the status is not returned success, which is happening in your case from the error log "appMemAddrTranslate(): Error in CSL_ratConfigRegionTranslation()"

    Now the root cause of this issue why there is a rat configuration error is because of the below statement in ${PSDK_RTOS}/pdk_j784s4_09_01_00_22/packages/ti/csl/src/ip/rat/V0/priv/csl_rat.c

    Here, your region size is which is 512 MB (0x20000000) and the baseaddress of DDR_SHARED_MEM (when 8MB) is 0xC0000000 which is aligned to 512MB.

    But the base address of DDR_SHARED_MEM (when 128MB) is 0xC7800000, which is not aligned to 512MB, causing this error.



    Now what I did to check this is to reduce region size to 256 MB (0x10000000) and the baseaddress of DDR_SHARED_MEM (with 128MB and INTERCORE_ETH_DATA_MEM region increased from 24MB to 160MB  --> so that the baseaddress would also be increased from  0xC7800000 to 0xD0000000) is aligned to 256MB.

    This is working fine for me, and I don't see any error now.

     

    Hence, I would suggest you align the DDR_SHARED_MEM baseaddress to the region_size
    (DDR_SHARED_MEM_SIZE + UBOOT_RELOC_MEM_SIZE) and this should resolve your issue.

    Regards,

    Nikhil

  • Hi,

    Sorry, I don't quite understand what you mean,

    ddr_shared_mem_addr is a dynamically calculated value, how should I modify it?

    Can you give me some examples?

  • Hi,

    You would have 2 options here. 

    1. To adjust the memory that you are using such that the resulting ddr_shared_mem_addr would be aligned as per requirement.

    2. To hardcode the DDR_Shared_MEM to an address such that it is aligned as per requirement. Here you would have to ensure that the ddr_intercore_eth_data_addr + ddr_intercore_eth_data_size <  ddr_shared_mem_addr.

    Regards,

    Nikhil

  • Hi

    I prefer option 1 for subsequent adjustments.

    But I still don't know how to adjust the other memory.

    ddr_shared_mem_addr is the result of accumulation, when I modify mcu2_0_ddr_local_heap_size = 128*MB, why is the ddr_shared_mem_addr out of alignment?

  • Hi

    ddr_shared_mem_addr is the result of accumulation, when I modify mcu2_0_ddr_local_heap_size = 128*MB

    Yes, you are correct.

    Here, your region size is which is 512 MB (0x20000000) and the baseaddress of DDR_SHARED_MEM (when 8MB) is 0xC0000000 which is aligned to 512MB.

    But the base address of DDR_SHARED_MEM (when 128MB) is 0xC7800000, which is not aligned to 512MB, causing this error.

    As mentioned above, when your mcu2_0_ddr_local_heap_size = 8MB, the DDR_SHARED_MEM address is 0xC0000000. The address is aligned to 512MB.

    But when you increased the size of mcu2_0_ddr_local_heap_size = 128MB, the DDR_SHARED_MEM address is 0xC7800000. This is not aligned to 512MB. The only address that would align to 512MB (after 0xC0000000) is 0xE0000000.

    So, you would have to reduce the other regions between mcu2_0_ddr_local_heap and ddr_shared_mem by (0x7800000), so that the DDR_SHARED_MEM address is back to 0xC0000000.

    Regards,

    Nikhil

  • Thank you.

    I see what you mean,

    My area size is 512MB, so I can also increase the rest of the area between mcu2_0_ddr_local_heap and ddr_shared_mem (by 0x18800000) so that the DDR_SHARED_MEM address back to 0xE0000000,

    In this case, can it be implemented normally?

  • Hi,

    Yes. That could be done. 

    In this case, the size of DDR_SHARED_MEM is 480 MB and UBOOT is 32MB, and in the python script, the uboot address is hardcoded to 0xFC000000.

    If you get the DDR_SHARED_MEM  to 0xE0000000, then you would have to make u-boot reloc address as 0xFE000000.

    Regards,

    Nikhil

  • Thank you very much. My problem has been solved.