Hi Amy,
For the register address 0x29 you mention it produces same output as screenshot 1. Can you please let me know what is the screenshot1? Setting the register 0x29 to 0xF0 enabled the SYSREF processing, Enable the sysref receiver and also enable…
Part Number: ADC09DJ1300-Q1 Other Parts Discussed in Thread: ADC09DJ1300 , ADC09QJ1300 The datasheet shows that the ADC09DJ1300 is a 9-bit, 1,3G ADC that can be used for single, dual, and quad channels. I would like to ask a few questions.
1. What is the…
Part Number: ADC09DJ1300 Hi Experts,
Good day. Would like to ask assistance please.
For the part ADC09DJ1300AAVT, I could see multiple SNR values from D/S specifications:
Can you help us determine which from these values we have to take and why?
Thank…
Part Number: DAC37J82 Other Parts Discussed in Thread: ADC09DJ1300 Can you please advice of the ECCN export license classification for the following parts:
DAC37j82
ADC09dj1300
Part Number: LMK04828 Other Parts Discussed in Thread: ADC09DJ1300 , LMK04832 Hello,
Currently I try to connect SYSREF+/- differenctial pair of LMK04828 to that of ADC09DJ1300. I am thinking of using DC coupling of LVPECL interface because of JESD204B interface…
Part Number: ADC09QJ1300 Other Parts Discussed in Thread: ADC09DJ1300 , ADC12DJ2700 Hello guys,
I've been reading the datasheet of ADC09xJ1300 series ADCs, I wonder if it's possible to interleave multiple channels on a single chip to achieve a higher sample…
Part Number: TI-JESD204-IP I planning on using a ADC09DJ1300-BGA144 to send data to our existing SmartFusion2 FPGA. Need to understand if I can support JESD204-IP?