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Clock & timing

Clock & timing

Clock & timing forum

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Texas Instruments (TI) Clock & timing support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search clock & timing IC content or ask technical support questions on everything from clock synchronizers and generators to clock buffers and timers. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.

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Frequent questions
  • [FAQ] LMK5B33216: Determining impact of supply voltage noise and PSNR specification on output phase noise

    Timothy T
    Timothy T
    Part Number: LMK5B33216 This covers the math to simulate clock output phase noise noise as a result of voltage supply noise using PSNR and then creating a voltage supply noise mask based on your requirements. How to use PSNR data and input voltage…
    • 1 day ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?)

    Jennifer Bernal
    Jennifer Bernal
    Part Number: LMK5B33216 [DPLL Training Slides] The What-How of TI DPLLs_share, e2e.pdf
    • 1 day ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] PLLATINUMSIM-SW: PLL Training Material

    Dean Banerjee
    Dean Banerjee
    Part Number: PLLATINUMSIM-SW Attached is a detailed training on PLL Theory PLL Fundamentals Full Training (Public).pdf
    • 2 days ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] LMK5B33216: How to choose the loop bandwidth for your PLL

    Timothy T
    Timothy T
    Part Number: LMK5B33216 Here's some information on choosing a loop bandwidth for your PLL to optimize noise performance. The presentation starts with some general theory on noise and PLLs, discusses how to pick loop bandwidth for a "PLL/VCO optimized…
    • 2 days ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TLC555: What are the performance differences expected for TLC555 PCN 20231130002.1?

    Ron Michallick
    Ron Michallick
    Part Number: TLC555 Other Parts Discussed in Thread: , TLC3555-Q1 , TLC3555 Tool/software: PCN 20231130002.1 is the “Qualification of RFAB using qualified Process Technology, Die Revision, Datasheet update and additional Assembly Site/BOM options…
    • Answered
    • 4 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Does TI have crosses for obsolete Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987 as per the Product Discontinuance Notice issued by ADI on March 22, 2022?

    Vibhu  Vanjari
    Vibhu Vanjari
    TI’s wide portfolio of RF PLLs & synthesizers features devices that are potential crosses for Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987. With most of TI’s RF PLLs & synthesizers…
    • over 3 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TPL5010: How to disable the watchdog function of TPL5010

    Dong Shen1
    Dong Shen1
    Part Number: TPL5010 Hi all, I am a FAE of TI,now my customer has a watchdog disabled problem, so I synchronously ask you for a solution: Problem Description: the customer's MCU wants to disable the watchdog function during the recording program…
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: How to connect the unused pins?

    Kia Rahbar
    Kia Rahbar
    When a pin on my clock buffer is not being used, what is the correct termination?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: Can my buffer handle an input while it is powered off?

    Aaron Black
    Aaron Black
    If my buffer is powered off can an input go into the device without damaging it?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: How to deal with the unused output differential pin in a RF synthesizer?

    Noel Fung
    Noel Fung
    I need single-ended output, how to deal with the unused output differential pin?
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
>

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  • Not Answered

    [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?) 0

    33 views
    1 reply
    Latest 1 day ago
    by Timothy T
  • Suggested Answer

    LMK04808: LMK04808 : Design Queries 0

    37 views
    3 replies
    Latest 1 day ago
    by Nachiketh Karanth
  • Not Answered

    CDCE62005: need help provide IC example code 0

    31 views
    2 replies
    Latest 1 day ago
    by Haiwen Huang
  • Not Answered

    LMK04832EVM: LMK04832 Outputs – Phase Alignment on All Device Clock output Across Multiple Output Formats 0

    30 views
    1 reply
    Latest 1 day ago
    by Michael Srinivasan
  • Suggested Answer

    LMK03318: 1GHz Clock Input 0

    58 views
    3 replies
    Latest 1 day ago
    by Michael Srinivasan
  • Suggested Answer

    LMK1C1104: Current consumption 0

    18 views
    1 reply
    Latest 1 day ago
    by Michael Srinivasan
  • Suggested Answer

    CDCLVP111-EP: Input biasing 0

    45 views
    3 replies
    Latest 1 day ago
    by Michael Srinivasan
  • Not Answered

    [FAQ] LMK5B33216: Determining impact of supply voltage noise and PSNR specification on output phase noise 0

    24 views
    0 replies
    Started 1 day ago
    by Timothy T
  • Not Answered

    LMK04828BEVM: PLL not locked 0

    110 views
    6 replies
    Latest 1 day ago
    by Michael Srinivasan
  • Suggested Answer

    LMK04828: HSDS output common mode level 0

    246 views
    12 replies
    Latest 1 day ago
    by Markus Sporer
  • Not Answered

    DRA821U: DRA821U: SRAM write issue 0

    163 views
    12 replies
    Latest 2 days ago
    by Subashini N
  • Not Answered

    LMK3H2108: Request for support on restricted variant LMK3H2108A16RKPR 0

    61 views
    2 replies
    Latest 2 days ago
    by jerry ong
  • Answered

    LMX2594EVM: Ramp using lmx2594 0

    48 views
    2 replies
    Latest 2 days ago
    by sathish kumar j
  • Not Answered

    LMK5B33414EVM: 1PPS jitter cleaner with Zero Delay Mode typical configuration example 0

    197 views
    4 replies
    Latest 2 days ago
    by Connor Lewis
  • Not Answered

    [FAQ] PLLATINUMSIM-SW: PLL Training Material 0

    51 views
    0 replies
    Started 2 days ago
    by Dean Banerjee
  • Not Answered

    [FAQ] LMK5B33216: How to choose the loop bandwidth for your PLL 0 Locked

    53 views
    0 replies
    Started 2 days ago
    by Timothy T
  • Not Answered

    LMK01000: lmk01000 lifecycle 0

    31 views
    1 reply
    Latest 2 days ago
    by Connor Lewis
  • Answered

    LMX2572LP: Modulation sidebands LMX 2572LP 0

    116 views
    4 replies
    Latest 2 days ago
    by Dirk Wichmann
  • Suggested Answer

    LMX1205: LMX1205 Programming related queries, Differential input voltage swing 0

    162 views
    3 replies
    Latest 3 days ago
    by Noel Fung
  • Suggested Answer

    LMX1205: CLKIN_P & CLKIN_N Differential input Voltage swing related 0

    114 views
    3 replies
    Latest 3 days ago
    by Noel Fung
>