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Clock & timing

Clock & timing

Clock & timing forum

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Texas Instruments (TI) Clock & timing support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search clock & timing IC content or ask technical support questions on everything from clock synchronizers and generators to clock buffers and timers. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.

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Frequent questions
  • [FAQ] LMK5B33216: Determining impact of supply voltage noise and PSNR specification on output phase noise

    Timothy T
    Timothy T
    Part Number: LMK5B33216 This covers the math to simulate clock output phase noise noise as a result of voltage supply noise using PSNR and then creating a voltage supply noise mask based on your requirements. How to use PSNR data and input voltage…
    • 6 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?)

    Jennifer Bernal
    Jennifer Bernal
    Part Number: LMK5B33216 [DPLL Training Slides] The What-How of TI DPLLs_share, e2e.pdf
    • 6 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] PLLATINUMSIM-SW: PLL Training Material

    Dean Banerjee
    Dean Banerjee
    Part Number: PLLATINUMSIM-SW Attached is a detailed training on PLL Theory PLL Fundamentals Full Training (Public).pdf
    • 6 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] LMK5B33216: How to choose the loop bandwidth for your PLL

    Timothy T
    Timothy T
    Part Number: LMK5B33216 Here's some information on choosing a loop bandwidth for your PLL to optimize noise performance. The presentation starts with some general theory on noise and PLLs, discusses how to pick loop bandwidth for a "PLL/VCO optimized…
    • 6 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TLC555: What are the performance differences expected for TLC555 PCN 20231130002.1?

    Ron Michallick
    Ron Michallick
    Part Number: TLC555 Other Parts Discussed in Thread: , TLC3555-Q1 , TLC3555 Tool/software: PCN 20231130002.1 is the “Qualification of RFAB using qualified Process Technology, Die Revision, Datasheet update and additional Assembly Site/BOM options…
    • Answered
    • 10 months ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Does TI have crosses for obsolete Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987 as per the Product Discontinuance Notice issued by ADI on March 22, 2022?

    Vibhu  Vanjari
    Vibhu Vanjari
    TI’s wide portfolio of RF PLLs & synthesizers features devices that are potential crosses for Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987. With most of TI’s RF PLLs & synthesizers…
    • over 3 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] TPL5010: How to disable the watchdog function of TPL5010

    Dong Shen1
    Dong Shen1
    Part Number: TPL5010 Hi all, I am a FAE of TI,now my customer has a watchdog disabled problem, so I synchronously ask you for a solution: Problem Description: the customer's MCU wants to disable the watchdog function during the recording program…
    • Answered
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: How to connect the unused pins?

    Kia Rahbar
    Kia Rahbar
    When a pin on my clock buffer is not being used, what is the correct termination?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] Clock Buffers: Can my buffer handle an input while it is powered off?

    Aaron Black
    Aaron Black
    If my buffer is powered off can an input go into the device without damaging it?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
  • [FAQ] RF synthesizers: How to deal with the unused output differential pin in a RF synthesizer?

    Noel Fung
    Noel Fung
    I need single-ended output, how to deal with the unused output differential pin?
    • Answered
    • over 5 years ago
    • Clock & timing
    • Clock & timing forum
>

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  • Not Answered

    Replace Renesas & SiTime Data Center PCIe Clocking Solutions with TI Buffers & Oscillators. 0

    580 views
    0 replies
    Started 2 months ago
    by CP Ong
  • Not Answered

    [FAQ] The What and How of TI DPLLs (What is a DPLL? How does a DPLL work?) 0

    999 views
    1 reply
    Latest 6 months ago
    by Timothy T
  • Not Answered

    LM567C: Frequency Capture 0

    0 views
    0 replies
    Started 17 minutes ago
    by Aakash K
  • Not Answered

    LMX2571EVM: LMX2571- PLL SETTLING TIME 0

    13 views
    0 replies
    Started 14 hours ago
    by CAREY
  • Not Answered

    TLC555-Q1: Can TLC555-Q1 make t_w as 20 minutes? 0

    58 views
    6 replies
    Latest 22 hours ago
    by Ron Michallick
  • Not Answered

    LMK3H0102: Part with 1.2V IO/VCC 0

    99 views
    11 replies
    Latest 23 hours ago
    by Sandra Saba
  • Suggested Answer

    LMX2572: SYNC timing relative to LOCK 0

    43 views
    2 replies
    Latest 1 day ago
    by John Roulston
  • Answered

    CDCE6214: CDCE6124 syntonized clock servo 0

    391 views
    19 replies
    Latest 1 day ago
    by Tobias Greuter
  • Not Answered

    LMX2572: Cat3 phase sync not reliable +1

    46 views
    1 reply
    Latest 1 day ago
    by Alessandro Spinetti1
  • Not Answered

    LMX2820EVM: LMX2820 VCO calibration process 0

    26 views
    2 replies
    Latest 1 day ago
    by Gombo Tsydynzhapov
  • Suggested Answer

    LMX2594: Regarding the output power of the LMX2594 0

    81 views
    7 replies
    Latest 1 day ago
    by Yabe Masami
  • Suggested Answer

    LMK00105: 2:1 single-ended low-jitter MUX solution 0

    35 views
    1 reply
    Latest 1 day ago
    by Michael Srinivasan
  • Answered

    LMH1981: HSync jitter issue under open termination & question about allowable DC offset before AC coupling 0

    110 views
    5 replies
    Latest 1 day ago
    by Noel Fung
  • Not Answered

    CDCLVP1102: require pin 1 to be positioned at Q1 0

    37 views
    3 replies
    Latest 1 day ago
    by Michael Srinivasan
  • Suggested Answer

    LMX2571: FSK_SPI Hold time issue 0

    12 views
    1 reply
    Latest 1 day ago
    by Noel Fung
  • Answered

    LMK5C23208A: 1PPS output as SYNC trigger 0

    29 views
    3 replies
    Latest 1 day ago
    by Jaryd Dukes
  • Not Answered

    LMX2594: LMX2594 related issues 0

    9 views
    1 reply
    Latest 2 days ago
    by Noel Fung
  • Answered

    CDCE6214: Unused REF input 0

    22 views
    1 reply
    Latest 2 days ago
    by Jaryd Dukes
  • Suggested Answer

    LMX2594: Latest version of the PLL product 0

    26 views
    1 reply
    Latest 2 days ago
    by Noel Fung
  • Not Answered

    LMK04828: The phase of SYSREF (SDCLK) and CLK (DCLK) has shifted 0

    15 views
    1 reply
    Latest 2 days ago
    by Derek Payne
>