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LMX2582EVM: LMX2582 EVM phase noise degradation when programmed with external microcontroller and integrated with system

Part Number: LMX2582EVM
Other Parts Discussed in Thread: LMX2582, USB2ANY

Tool/software:

Dear Sir,

We have purchased the LMX2582 eval board so that we can evaluate the performance before using it in the system. After evaluation, we have developed the PCB as per Gerber provided by you for eval with the simple addition of an uC on the same PCB for programming.

We are using two LMX 2582 developed as per Gerber provided for EVAL in a cascade where one acts as a reference clock and another as LO for the Mixer. The first LMX2582 module is programmed with external uC. Individually standalone when the results are checked the phase noise appears acceptable for the first LMX2582 but after cascading the second LMX2582 phase noise is degrading at 10KHz suddenly since last week, it was working fine even when cascaded. The results are still fine if we simply program the first LMX2582 using USB2ANY and TI GUI in cascade. The phase noise at 10 KHz offset is dropping from -112 dBc/Hz to -93 dBc/Hz at 1205 MHz.  

We do not understand what is the reason that is causing the issue, please guide us. Let me know if you need any supporting documents.

Below is the PCB image with uC removed and PLL programmed using USB2ANY. The connector we made was based on pin data.

The schematic for the above board is attached below:

Ref_Clk_Gen.pdf

In the above case, the cascaded phase noise is acceptable as shown below,

When the uC is either connected to PCB or we even tried connecting the uC on a separate PCB and programmed the PLL through the connector to check if the uC is a problem or the placement of the uC is a problem, but even when the uC is connected outside the cascaded phase noise is degraded. The results are degraded even after replacing or changing the uC with a different version. The degraded results are shown below:

The results are fine only when the first uC is completely disconnected from the system or programmed from USB2ANY.

We have used the default loop filter of the EVAL board in our design.

For the first LMX2582 (40MHz to 120.5 MHz), the following is the register file used. This is the LMX where the uC issue is observed. We have tested the register files using two controllers namely:

Controller 1: STM32F042F6P6
Controller 2: STM32F429ZIT6U(STM32F4-discovery)

R70	0x460000
R69	0x450000
R68	0x440089
R64	0x400077
R62	0x3E0000
R61	0x3D0001
R59	0x3B0000
R48	0x3003FC
R47	0x2F00CF
R46	0x2E0AA1
R45	0x2D00C8
R44	0x2C0000
R43	0x2B0000
R42	0x2A0000
R41	0x2903E8
R40	0x280000
R39	0x278104
R38	0x260060
R37	0x254000
R36	0x240C41
R35	0x23119B
R34	0x22C3EA
R33	0x212A0A
R32	0x20210A
R31	0x1F0601
R30	0x1E0034
R29	0x1D0084
R28	0x1C2924
R25	0x190000
R24	0x180509
R23	0x178842
R22	0x162300
R20	0x14012C
R19	0x130965
R14	0x0E0DEC
R13	0x0D4000
R12	0x0C7001
R11	0x0B0018
R10	0x0A10D8
R9	0x090302
R8	0x081084
R7	0x0728B2
R4	0x041943
R2	0x020500
R1	0x010808
R0	0x00221C

The register file used for the second LMX2582 (120.5 MHz to 1205 MHz) is attached below. The Controller used here is STM32F04ZIT6.

R70	0x460000
R69	0x450000
R68	0x440089
R64	0x400077
R62	0x3E0000
R61	0x3D0001
R59	0x3B0000
R48	0x3003FC
R47	0x2F00CF
R46	0x2E0A21
R45	0x2D0000
R44	0x2C0000
R43	0x2B0000
R42	0x2A0000
R41	0x2903E8
R40	0x280000
R39	0x278104
R38	0x260028
R37	0x254000
R36	0x240C21
R35	0x23029B
R34	0x22C3EA
R33	0x212A0A
R32	0x20210A
R31	0x1F0601
R30	0x1E0034
R29	0x1D0084
R28	0x1C2924
R25	0x190000
R24	0x180509
R23	0x178842
R22	0x162300
R20	0x14012C
R19	0x130965
R14	0x0E0DEC
R13	0x0D4000
R12	0x0C7001
R11	0x0B0018
R10	0x0A10D8
R9	0x090302
R8	0x081084
R7	0x0728B2
R4	0x041943
R2	0x020500
R1	0x010808
R0	0x00229C


  •  can you guide us on this? Any guidance would be helpful

  • Hi Akshay,

    Can you verify the first synthesizer output with USB2ANY and MCU?

  • Yes, we compared both, The following are the results,

    Below is the result with USB2ANY

    Below is the result with MCU

    Both appear to be acceptable, with 3dBc variation observed in a 10KHz offset.

  • Hi Akshay,

    With your configuration and settings, assuming a noiseless 40MHz reference clock, the phase noise of the first board will look like below.

    Your data is higher than simulation because the reference clock is not noiseless and the test equipment does not have low enough noise floor.

    Any way, if you use this output as the reference clock to the second board, you will get below phase noise.

    Basically, the output phase noise is dominated by the reference clock. In other words, the phase noise of the first board must be very good, otherwise the phase noise of the second board will be affected.

    Back to the original question, why is the phase noise worst with MCU? I don't know. If the 40MHz reference clock is an external source (e.g. signal generator), then the MCU shall take the full responsibility to the phase noise degradation. If you have a high frequency probe, you can probe the MCU to see if it generates noise. 

    In your layout, do you have any digital traces run underneath the loop filter?

  • Thank you for the response and for taking the time to investigate our issue.

    We could diagnose the issue and even correct it. The reset register was not programmed as per the recommended sequence. The cascaded phase noise is restored after correcting the reset register programming sequence even when programmed with MCU.