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LMX2582: Phase noise degradation

Part Number: LMX2582


Dear Sir,

We suffered phase noise degradation at frequency offset >100KHz. The RF frequency is 4.675GHz. The degradation over frequency is:

(1) 1KHz offset: 0dB degradation. Measurement is same as phase noise simulation.  

(2) 10KHz offset: 4dB degradation. Measurement is 4dB worse than phase noise simulation.  

(3) >100KHz offset: 8dB degradation. Measurement is 8dB worse than phase noise simulation.  

The loop BW is ~45KHz. Since mainly degradation is manily at frequency range > loop BW, so I suspected the degradation comes from VCO. VCO voltage supply is TI's extra low noise LDO. I tried to add more 22uF capacitors at VCO voltage bus, but there is no improvement. Could you please share your comment? What is possible root cause?

Tony

   

 

  • Hi Tony,

    Can you tell us your loop filter value?

  • Dear Sir, 

    Please refer to loop filter as below.

    Tony

  • Hi Tony,

    The problem is likely due to C4 being too small. If you let PLL Sim to calculate the loop filter value to you, you will always get a ≥3.3nF C4. 

    The last loop filter shunt capacitor connecting to the Vtune pin should be at least 3.3nF, otherwise the VCO phase noise between 10kHz and 20MHz offset will be bad. We are about to put his requirement in the datasheet. Sorry for the inconvenience caused.

  • Dear Sir,

    We had followed your recommendation to modify loop filter. Loop BW was slightly changed from 45KHz to 36KHz. Phase noise at 1MHz is similar to datasheet now. Phase noise at 100KHz is improved, but still worse than simulation. The degradation over frequency is:

    (1) 1KHz offset: 0dB degradation originally => No change

    (2) 10KHz offset: ~4dB degradation originally => No change

    (3) 100KHz offset: ~8dB degradation originally => ~4dB degradation now.   

    (3) 1MHz offset: ~8dB degradation originally => 0dB degradation now.

    Is there other recommendation from you? The attached file is register setting. RF frequency is 4675MHz. Reference is 10MHz. Please kindly review the setting and comment. 

    R64	0x400177
    R62	0x3E0000
    R61	0x3D0001
    R59	0x3B0000
    R48	0x3003FC
    R47	0x2F08C0
    R46	0x2E1EA3
    R45	0x2D0003
    R44	0x2C0000
    R43	0x2B0000
    R42	0x2A0000
    R41	0x290004
    R40	0x280000
    R39	0x278204
    R38	0x26005C
    R37	0x254000
    R36	0x240011
    R35	0x23021D
    R34	0x22C3CA
    R33	0x212A0A
    R32	0x20210A
    R31	0x1F0401
    R30	0x1E0034
    R29	0x1D0084
    R28	0x1C2924
    R25	0x190000
    R24	0x180509
    R23	0x178842
    R22	0x162300
    R20	0x14012C
    R19	0x130AF5
    R14	0x0E0FFC
    R13	0x0D4000
    R12	0x0C7001
    R11	0x0B0018
    R10	0x0A12D8
    R9	0x090302
    R8	0x083084
    R7	0x0728B2
    R4	0x041943
    R2	0x020500
    R1	0x010808
    R0	0x00220C
    

    Tony

  • Hi Tony,

    How is the phase noise of your 10MHz reference? Is it a sine wave or square wave?

  • Dear Sir,

    It is square wave.

    Tony

  • Hi Tony,

    Square wave is good as its slew rate is high.

    Do you have the phase noise plot of the 10MHz reference clock?

  • Dear Sir,

    Please refer to attached files for the 10MHz phase noise, loop filter, measurement result and register setting.

     toTI_Tx PN_LMX2582 (PFD 50M BW 10K) 060821.pptx 

    R64	0x400177
    R62	0x3E0000
    R61	0x3D0001
    R59	0x3B0000
    R48	0x3003FC
    R47	0x2F08C0
    R46	0x2E1EA3
    R45	0x2D0003
    R44	0x2C0000
    R43	0x2B0000
    R42	0x2A0000
    R41	0x290004
    R40	0x280000
    R39	0x278204
    R38	0x26005C
    R37	0x254000
    R36	0x240011
    R35	0x23021D
    R34	0x22C3CA
    R33	0x212A0A
    R32	0x20210A
    R31	0x1F0401
    R30	0x1E0034
    R29	0x1D0084
    R28	0x1C2924
    R25	0x190000
    R24	0x180509
    R23	0x178842
    R22	0x162300
    R20	0x14012C
    R19	0x130AF5
    R14	0x0E0FFC
    R13	0x0D4000
    R12	0x0C7001
    R11	0x0B0018
    R10	0x0A12D8
    R9	0x090302
    R8	0x083084
    R7	0x0728B2
    R4	0x041943
    R2	0x020500
    R1	0x010808
    R0	0x00220C
    

    Please provide your simulation result for my reference. Please also share your comment for bad phase noise issue.

    Tony 

  • Hi Tony,

    Since the loop bandwidth is just 6kHz, you don't need to enable the MULT to make fpd=50MHz. Whenever MULT > 1, the MULT will add noise to the PLL.

    Here is my sim file with the reference clock noise included.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/e2e_5F00_2582.sim

    when you modify the loop filter in your board, make sure to put C3 close to the Vune pin. 

    4675MHz is a fractional channel, in TICS Pro, you may need to find the optimum MASH_ORDER. Usually, 3rd order is good for most of the use cases. PFD_DLY needs to match with the MASH_ORDER, mouse-over the PFD_DLY pull-down menu to see application tips.

  • Dear Sir,

    Phase noise is getting better now. We have another issue regarding to noise density when PLL frequency is 4675 GHz. The noise density is ~-141dBm/Hz at O/P power 3dBm that is much higher than your datasheet (~ -150dBm/Hz). Could you please share your comment? What is possible root cause?

    Tony

  • Dear Sir,

    Phase noise is getting better now. We have another issue regarding to noise density when PLL frequency is 4675 GHz. The noise density is ~-141dBm/Hz at O/P power 3dBm that is much higher than your datasheet (~ -150dBm/Hz). Please refer to attached file in detail. Could you please share your comment? What is possible root cause?

    Tony

  • Hi Tony,

    We specified the noise floor in dBc/Hz at an offset of 100MHz. You were measuring the noise density at offset over 690MHz.

  • Dear Noel,

    OK. Is noise density -141dBm/Hz at 690MHz offset correct? Can you check on your evaluation board? Please also recommend how to improve this.

    Tony

  • Hi Tony,

    The marker is at 3976.2MHz. Could you set the center frequency to 3976.2MHz and span =1MHz (or 10MHz). Power up/down LMX2582 with the POWERDOWN bit, do you see any noise floor difference?