Part Number: ADC12QJ1600-Q1 Hello,
I intend to design a board with X8 ADCQJ1600 devices connected to an FPGA - each ADC is connected to an FPGA through four
differential lanes ( 12 bit 64/66b JMODE 8 ). The ADC sampling rate is 1 GHZ.
My questions are…
Part Number: ADC12QJ1600-Q1 Other Parts Discussed in Thread: ADC12QJ1600 hello,
Just got from TI the "TI204C-IP-Release-v1.11-LATEST.zip"
Is this package is "good" to the ADC12QJ1600 chip?
Regards,
Giora
Part Number: ADC12QJ1600-Q1 Other Parts Discussed in Thread: ADC12QJ1600 I know that the ADC12QJ1600 is not listed as a safety compatible/compliant device, but I hoping that you have basic information such as its raw FIT rate and failure mode distribution…
Part Number: ADC12QJ1600-Q1 Hi There,
The FPGA core clock setting and relationship with sample rate. ADC12QJ1600-Q1 has 1 GSPS but both FPGA Core Clock is 250 MHz. Please explain how it works.
Other Parts Discussed in Thread: LMH32404 , ADC12QJ1600 Hello,
I am looking to purchase "LMH32404 - Q1 interface board for ADC12QJ1600 EVM Board" (see picture).
but I can not found it on TI site.
any body can help?
Regards,
Giora
Part Number: ADC12QJ1600-Q1 Other Parts Discussed in Thread: ADC12QJ1600 Hi, experts,
I'm assessing the ADC12xJ1600 for our LiDAR project, now I have 2 issues, could you please help me check in details? thanks a lot.
1. internal CPLL output jitter…
Part Number: TSW14J58EVM Other Parts Discussed in Thread: TSW12QJ1600EVM , , ADC12QJ1600 , ADC12QJ1600-Q1 Hello,
I have TSW14J58EVM DC182_A10, and TSW12QJ1600EVM evaluation boards. I followed the steps from Chapter 3 (SLAU796-July 2020) "SETUP PROCEDURE…
Part Number: ADC09QJ1300-Q1 Other Parts Discussed in Thread: ADC12QJ1600 , , ADC09QJ1300 hi，
The AMI simulation model for ADC09QJ1300-Q1 on TI's official website is ADC12QJ1600. Can ADC09QJ1300-Q1 also be used? If not possible, could you please help provide…
Part Number: ADC12QJ1600-Q1 In ADC12QJ1600-Q1 datasheet , under GAIN_TRIM Register two different description is given as Gain DAC Trim and This register trims the gain of all ADC cores. here DAC and ADC terms confuses me, please let me clear on this.
