Part Number: ADC34J43EVM Other Parts Discussed in Thread: LMK04828 , In ADC34J43EVM, it seems some power pins for LMK04828 are designed to share same power rails. What's the reason to do like this?
Part Number: ADC34J43EVM I find on the board's JESD interface, beside CLK*, SYSREF*, there is another clock called 'JESD CORECLOCK'. What's the usage of it? I want to use it with Xilinx FPGA, so I wonder if this is mandatory for Xilinx JESD IP Core?…
Part Number: ADC34J43EVM
I don't understand well about this.
SYNCP and SYNCM of the board are intended to DC coupling with LVDS, right? But CLK and SYSREF are intended to LVPECL AC coupled, why SYNC is LVDS DC coupling? And the datasheet says the…
Part Number: ADC34J43EVM Other Parts Discussed in Thread: ADC34J43 Hello,
A question please, about the SPI communication to the ADC34J43 EVM:
I wish to configure the ADC from an external FPGA, assembled on a different board. I saw that there is a jumper…
Part Number: ADC34J43EVM Other Parts Discussed in Thread: TSW14J50EVM , Dear TI E2E,
I have two problem which using ADC34J43EVM and capturing by TSW14J50EVM.
I follow the ADC3xxx, ADC3xJxx EVM User’s Guide to setting EVM broad, ADC3000 GUI, and HSDC Pro…
Part Number: LMK04832 Other Parts Discussed in Thread: ADC34J43 , ADC34J43EVM I'm designning a board based on lmk04832 and adc34j43, taking ADC34J43EVM as reference. And I feel the termination schema is like a black box, especially for LCPECL output. I…
Part Number: ADC34J43 Other Parts Discussed in Thread: LMK04832 , , , LMK04828 I'm planning a DAQ system with ADC34J43 + LMK04832 + FPGA. And take ADC34J43EVM as reference.
My target sample rate is 80M. So, the clock goes to the 'CLKP' and 'CLKM' should…
Hi Diverger,
I believe both 2.5 and 1.8V based LVDS still have the same common mode (1.25V) and differential swing (350 mV), so use which ever one is more convenient for your FPGA. On the ADC34J43EVM, I am able to establish the JESD link without the level…
