Part Number: ADS5402 Other Parts Discussed in Thread: ADS5401 , Are there any routing guidelines for the ADS5401 or ADS5402? I specifically interested in the differential data outputs and 1) What tolerance does each data diff pair within a channel have…
Part Number: ADS5402 The ground pins on the upper half of the part (like rows 10-14) seem like they really want to be analog ground since that is where the AVDD22, AVDD18, and INA_P/N powers and IF are. What would happen if those GND pins surrounding…
Part Number: ADS5402 Other Parts Discussed in Thread: CDCE72010 Dear colleague,
Our customer wants to give 800MHz clock to ADS5402, could you please give a recommendation clock device for ADS5402?
Thanks a lot!
Best Regards,
Rock Su
Part Number: CDCE72010 Other Parts Discussed in Thread: ADS5402 , CDCE6214-Q1 , LMK03318 , CDCE913 , LMK05318 Hi colleague,
Out customer is finding clock for ADS5402, and our DC colleague reply is in below:
https://e2e.ti.com/support/data-converters/f/73/p…
Part Number: ADS5402 I am working to build PCB board with ADS5402 that will be attached to Micronized Som board, and I am trying to reduce the output wires as much as I can .
Is it passable to convert ADS5402 from DDR LVDS output to single ended?
If not…
Part Number: ADS5402 Hello!
Trying to turn on test pattern output on ADS5402 ADC. According to datasheet, I only need to disable HP mode (by writing 0x8200 to register 0x01) and then set pattern through writing to registers 3C, 3D and 3E. But when I…
Part Number: ADS5402 Hi,
I would like to know about sampling rate.
My understanding is as below;
- Without interleaving correction, sampling rate of ADS5402 is same with input clock frequency .
- With interleaving correction, sampling rate of ADS5402…
Part Number: ADS5402 Hello!
In the datasheet on ADS5402 in the description (page 4) of the pin DBCLKP/N it says “Optionally Bus B can be latched with DACLKP/N "
However, I could not find in the documentation how to do it. Please tell me how…
Part Number: ADS5402 Hello!
ADC 5402 has a decimation mode. This is described in the datasheet on the ADC in Figure 38.
What frequency will be at the outputs of DACLKP(N) and what mode (DDR or SDR) will be when the decimation mode is on?
