Part Number: ADS5409 Tool/software: Hi team,
Our project uses xilinx Artix 7 FPGA interfaced with ADS5409 chip. Here, FPGA acts as the SPI master and ADC chip acts as the slave. We need to constraint the SPI interface using the below constraints
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Part Number: ADS5409 Other Parts Discussed in Thread: ADS5402EVM Tool/software: Hi Team,
Input to ADC clock pin is generated from external source. Instead of using SMA and balun circuit for single to differential conversion.
Can you please suggest…
Part Number: ADS5409 Other Parts Discussed in Thread: ADS5402EVM , , ADC12DL3200 , LMK04832 , LMK04828 , LMK61E08 Tool/software: Hi Team,
1) In the below image of ADS5402EVM, Pin number P10, N10 are used as trigger pin function. But in datasheet it…
Part Number: ADS5409 My customer is having a problem with the temperature readback from the ADS5409.
They're accessing the ADC via its 3-wire SPI port and have no problem accessing other internal registers.
No evidence of a problem with the SPI. …
Part Number: ADS5409ADS5409 has a SYNCp/n (LVDS differential pair) which forces the DDR output clock into a determinate state.
The datasheet (p.25) says that the SYNC signal is registered on the rising edge of CLKIN - the ADC sample clock.
Is there…
Part Number: ADS5409EVM Other Parts Discussed in Thread: ADS5402EVM , ADS5409 The ADS5409EVM (same as ADS5402EVM) appears to be driving the ADC’s SCLK, SDIO, and SDENB pins with 3.3V levels in violation of the ADC’s absolute maximum input voltage levels…
Part Number: ADS5409 Other Parts Discussed in Thread: ADS5400 , , ADS54J60 We have the following requirements in a Measurement system where we are considering usage of either ADS5409 or ADS5400:
1) 4mV – 1Vpk-pk differential input amplitude support…
Part Number: ADS5409 Hi Team,
I have a question that I'd like to get your help on regarding the ADS5409.
My customer is wondering if applying a differential signal less than 3.3V to the input pins before its supply voltage rails come up has the potential…
Hey Chuck,
Here is everything the sytems engineer could find on this device. We have not been able to get ahold of the design team for this chip. All of the sleep mode information i currently have on this device is seen below.
