Part Number: AM67 Hello, I was informed by Michael S. that the AM67 OSPI does not support multiple devices on a bus, however I only found references for AM62 and AM64. So the suggestion is to either source both clocks from a fanout or as long as our board…
Part Number: AM67 Hi all, We intend to configure the OLDI as extra GPIO on the AM67. GPIO1_X Also could we have some clarification regarding the LVCMOS 1.8V? My colleague noticed that there is VIH Steady State, and a VIH (standard). What does this imply…
Part Number: AM67 Hi,
since the ISP requires two dcc binaries (i.e. viss and 2a) as input files, we are wondering if can we generate these files locally on AM67? Based on AM6xA ISP Tuning Guide (Rev. A) : It seems that the TI's Reference Imaging Software…
Part Number: AM67 Hi TI team, Seems there is a discrepancy with the load calculation for the AM67. The equation your AM67 datasheet is displaying right below figure 6-18 seems to not follow the standard equation C_L = ((C_L1 * CL*2)/(C_L1 + C_L2)) + C_stray…
Part Number: AM67 Hi TI team, We have a question regarding the power down sequence for the AM67. We would like to clarify what the diagonal lines mean on the waveforms. Are these different ramp times that the supplies can shut off in the waveform? i.e…
Part Number: AM67 Hello TI Team, I am looking for the AM67 REFCLK IBIS and IBIS AMI models for PCIE and SGMII. Within the standard models for the SERDES0/1_REFCLK pins, the models are set as NCs. Within the IBIS AMI models (PCIE and SGMII), there isn…
Part Number: AM67 Hello TI team, I have a question regarding the J722S IBIS model that is publically provided. From what I understand the IBIS model used for the Main Domain I2C0_XX called LVCMOS_V. I want to confirm if this is the correct model is to…
Part Number: AM67 Hello my team is interested in using Asynchronous and Synchronous clocking for SERDES. How is this appropriately defined in the TRM? I assume that asynchronous clocking utilizies Separate Reference Clock with Independent Spread (SRIS…
Part Number: AM67 Hello, we are currently setting up an AM67 to utilize SGMII and PCIE (SERDES0/SERDES1), and I want to use the EXT_REFCLK1 as a single source input, and output the source to both SERDES0 and SERDES1. I am not finding explicit details…
Part Number: AM67 Hello TI team, My colleague and I want to know what would happen if we were to apply power to an unpowered GPIO prior to sequencing. Could you possibly confirm if this would cause any issues?
