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Part Number: CDC-CDCM7005-CALC Hi,
I don't see the CDC-CDCM7005-CALC calculator file under CDC-CDCM7005-CALC Calculation tool | TI.com . Please direct me to the correct link or email it to me. Thanks
Part Number: CDC-CDCM7005-CALC Hello,
in CDC-CDCM7005-CALC, there is a parameter, Gain peaking. For considering loop stability, I think we can check phase margin typically, like phase margin has 60dB or like that.
Does gain peaking affect to loop stability…
Charles,
There are trade-off on performance that can be made by varying multiple parameters.
Have you looked at the PLL calculation tools?
www.ti.com/.../cdc-cdcm7005-calc
I am not certain that the labview version works with Windows 7. However the excel…
Other Parts Discussed in Thread: CDCM7005 , LMK04002 , CLOCKDESIGNTOOL , CDC-CDCM7005-CALC , ADS5474 Hi,
I am looking for the high performance(both jitter as well as phase noise) clock synthesizer and jitter cleaner, Kindly suggest that which chip will be…
Other Parts Discussed in Thread: CDCM7005-SP , CDC-CDCM7005-CALC Hello,
I would like to use the CDCM7005-SP between FPGA and an Aeroflex WizardLink interface:
For the TLK2711 a jitter less 40ps is needed. Measurements showed that the FPGA Clk (125MHz…
Other Parts Discussed in Thread: CDCM7005 Hello,
While using a custome prototype board. I am unable to have a lock on the clock while having a reference 48Mhz clock and a 48Mhz output unless I am using Cycle Slip Lock Window. However it doesn't seem to…
Hi Leandro,
Thanks for your detailed clarifications on query 1 & 2. Please clarify me further on the 3 & 4
>> 3) In the following screen shot, you can find the divider value you need to set into the device
I tried that "Texas Instruments…
Hi Johnny,
thanks for your interest in our product. You can find a phase noise calculator for the CDC(M)7005 under the following link:
http://www.ti.com/tool/cdc-cdcm7005-calc
This tool allows you different actions. According to the PLL divider values…
Part Number: AM5728 Hi,
I am trying to build a linux kernel image using the yocto tool. But it is giving some bitbake error that I am not able to solve.
I am attaching the log here,
Loading cache: 100% |########################################################################################################################################################################…
Eric,
I first verified that the AFE7070 EVM works with the TSW1400 using the default condition. See attached pdf. This should work as described.
For dual output clock you have to move the R18 to R25 - this will set the CLOCK IO from the AFE7070 to drive…
