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  • CDC208: Termal resistance

    Part Number: CDC208

    Here is a customer would like to know the junction thermal resistance of CDC208DW. Please share this information.

    Clock & timing forum Clock & timing

  • CDC208: IBIS Model

    Part Number: CDC208

    Hi, Staff

    Is it possible to provide the IBIS Model of CDC208DW?
    There seems to be no IBIS Model on the product homepage.

    best regards
    cafain

    Clock & timing forum Clock & timing

  • RE: CDC208

    Hi Timothy;

    Earlier, you wrote, in regards to the CDC208:

    > I'll notify someone else to see if they know more about the CDC208 output and recommended termination.

    I was wondering if you found anyone who had an accurate knowledge of the internal output impedance yet.

    Also: I did some capacitance calculations regarding the load I am expecting the CDC208 to drive.  My load is approximately ~112pF, max.  And, the clock frequencies I will be using are below 5MHz (with a wavelength longer than the entire clock path length).  Is it a safe assumption to assume the CDC208 can handle this load, without distortion of Trise and Tfall from the CDC208's clock outputs, and that therefore no buffering is needed?

    Thank you for your time,

    Robert Grube

    Clock & timing forum Clock & timing

  • RE: How to terminate unused single-ended clock output pins on the CDC208? Design of output load for used clock outputs?

    Please see post:
    e2e.ti.com/.../1843778
    Clock & timing forum Clock & timing

  • ADS1675 - Bad performance, lots of noise in the time domain

    I have an 8 channel ads1675 board connected to an fpga.  I am getting poor performance out of the chips and I think some of it might be related to the CLK input.  I'm running all chips in low speed mode and was able to vary the clock speed via a programmable PLL (CS2300 from Cirrus then running that to an OR gate SN74ACT32N to convert it to a 5v level).  When I get the sample rate of the converter above 800kHz, the noise goes to well below 18 bits. 

    The converter seems to be VERY sensitive to clock jitter.  The CS2300 has very little according to the data sheet, so I think the noise may be coming from my board layout.  I have a common clock trace with a via at each A/D converter.  When I put a capacitor on the clock trace I can get the noise down to about 18 bits, but it varies drastically, sometimes its 21 bits, sometimes it is 16. 


    Do you have any suggestions?  I'm thinking about designing a new rev of the board using the CS2300 and the CDC208 clock IC.  Do you think this would be a good way to convert from a 3.3v to a 5v clock?

    It says in the ADS1675 datasheet that the CLK line needs to be 5v and have a 1ns rise/fall time? 

    "For best performance, the CLK duty cycle should be very close to 50%. The rise and fall times of the clock should be less than 1ns and clock amplitude should be equal to AVDD"

    Is this even possible at 32 mhz?  All of the clock signals I've ever seen are a triangle wave at best when you get above a few megahertz and dont come close to reaching the power supply rails.  Do you have a chip recommendation?  I've looked heavily at the reference design since we have been having trouble with the noise level on our board and it doesnt look like there is any way the reference design meets the 1ns rise and fall times either. 

    Data converters forum Data converters

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