Part Number: CDC3RL02 Hi All,
CDC3RL02 has two parts.
CDC3RL02 B YFPR and CDC3RL02YFPR.
This is a difference by backside coating.
Does the presence or absence of backside coating affect performance (reliability test, etc.) ?
Best Regards, Koji Hayashi
Part Number: CDC3RL02 I've downloaded the CDC3RL02 datasheet rev Aug 2018, the datasheet still showing the MCLK absolute maximum rating at -0.3V minimum.
Part Number: CDC3RL02 the previous post stated that the CDC3RL02 can take in an AC-coupled signal. In this case, what is the expected clock output range? We do observed negative voltage at clock output with AC coupled clock input.
However, section 7.3…
Part Number: CDC3RL02 Hi Team, Changed the Cap from a 2.2uF 201 to a 2,2uF 402 package size and the oscillations stopped. We have no way of measuring the actual capacitance accurately at low temperature, so can we confirm with the chip designer that 1uF…
Part Number: CDC3RL02 Hi
I am using 2.2uF X5R 6V3 20% ceramic capacitor on VLDO (pin B1).
At low temperature ~0deg C the LDO oscillates at ~ 1.2MHz causing 1.2MHz spurs on the CLK output.
I am certain the capacitance value remains above the minimum required…
Part Number: CDC3RL02
Hi,
I designed my clock circuit using CDC3RL02, I have a question about MCLK_IN of this buffer.
Does the buffer accept an AC-coupled clock signal as input for MCLK_IN? (The input signal into MCLK_IN in my design is as AC-coupled…
Part Number: CDC3RL02 Dear BU experts,
Would you confirm below question ?
In datasheet, The min spec of CLDO is 1uF. Does this include the tolerance of cap(1uF) ? So, customer must use higher value than 1uF considering the cap's tolerance itself.. Right…
Other Parts Discussed in Thread: CDC3RL02 From email:
HI,
Do we have any docs on the recommended footprint for the CDC3RL02BYFPR ?
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Regards,
Sonia
Dear Experts,
To clock buffer output enable always, Is it okay to tie CLK_REQ pin to VLDO pin directly ?
I doubt it because VLDO is enabled by CLK_REQ.. Would you confirm to me ? Thanks,