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Hello,
I was unable to recreate the issue at 70C with our EVM. It's possible the capacitors used in your layout are causing the issue. As they are external components, we are not able to exhaust all possible combinations during testing. Here's what we…
Hello,
When trying to recreate the issue again today in the lab, we discovered that the source in my setup had an issue with the duty cycle. This is what caused the CDCE62002 to not be able to lock. Upon correcting the issue with the source, I had the…
Part Number: CDCE62002 Hi,
we are using cdce62002, for converting ref clock of 13MHz to a clock of 204.8MHz.
below is the configuration we are using.
the issue is that we are facing many spurs at the output (please see attached screenshot of spectrum analyzer…
Part Number: CDCE62002 Hello expert,
Do we have timing requirement between PD and VCC? I checked datasheet page 10 and there is #PD reqiurements but i didn't find the graph to specific point out the relation between VCC and #PD. Could you provide the graph…
Part Number: CDCE62002 Hi i have few quesitons related the datasheet instruction about EEPROM to RAM loading,
Cite from Datasheet -
Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM on the Rising edge of PD^. - Question…
Part Number: CDCE62002
This circuit is our current circuit. The maximum configuration can only output 166M.
What parameters need to be changed to configure to 300M output ?
Part Number: CDCE62002 Hello team,
Could you please help us to address VCO calibration issue?
After configuring:
Register0 : 0x52D00470
Rigister1: 0x907FBFE1,
I confirmed 126MHz and 63MHz LVDS was output.
However, PLL_LOCK remains L.Therefore, I tired…
Part Number: CDCE62002 Hi are using CDCE62002 for recovered clock jitter cleaner. As in development board we are giving LVCMOS input 31.4 MHZ but we dont see any output. Can you let us know how to resolve the issue.
The dev kit says:
T.The second input…
