• CDCE6214Q1TM: How to perform the initialization configuration for the CDCE6214Q1TM？

  

  Felix fugang

  TI Thinks Resolved

  Part Number: CDCE6214Q1TM Tool/software: HI ti The CDCE6214Q1TM clock generator is used to provide one differential clock and one single-ended clock for FPGA，clk input is 50MHz via the SECREF_P 1， Is the design of the circuit shown in the diagram…

  • 6 months ago
  • Clock & timing
  • Clock & timing forum

• CDCE6214Q1TM: CDCE6214Q1TM Clock frequency multiplier

  

  ALEX jack

  TI Thinks Resolved

  Part Number: CDCE6214Q1TM Hi TI I want to convert 76.8MHZ LVCMOS single-ended clock to 153.6MHZ LVDS differential clock using CDCE6214Q1TM，The signal link is shown in red line in the following figure，Route to the output using a frequency multiplier…

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE6214Q1TM: LVDS Clock distribution and buffer requirement

  

  Vinaayaka M

  Resolved

  Part Number: CDCE6214Q1TM Other Parts Discussed in Thread: CDC6C , LMK00334 , , SN74LVC2G17 , DS90LV028A , SN65LVDS2 , DS90LV018A , DS90LV017A , CDCE6214-Q1 , DS90LV001 , ADS1299 Tool/software: Hi Team, I was planning to use clock generator for my application…

  • Resolved

  • 5 months ago
  • Clock & timing
  • Clock & timing forum

• CDCE6214Q1TM: Different output frequency from Multiple output simultaneously.

  

  Krishna Kumar C

  TI Thinks Resolved

  Part Number: CDCE6214Q1TM Other Parts Discussed in Thread: CDCE6214 Hi, I am working on a Xilinx FPGA based board which has major interfaces like SFP (Optical communication) and PCIe Gen4. Below are my clocking requirements for the interfaces. 156…

  • over 2 years ago
  • Clock & timing
  • Clock & timing forum

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