Part Number: CDCE937 Other Parts Discussed in Thread: CDCE949 , CDCE925 , CDCE913 I am using CDCE937 for a new design. I want to use this part to generate 6 frequencies total, 2 frequencies per PLL using the associated dividers. My questions are as follows…
Part Number: CDCE913 Hi, I was trying to read registers from CDCE913 and values returned seemed wierd to me :
So I went on the forum and I vagly read the thread "CDCE913: I2C byte access to odd address" where I saw that register address where different…
Part Number: CDCE913 Other Parts Discussed in Thread: CDCM6208 , I have a table of frequencies that should be generated by CDCD913, and I want to use a 27mhz crystal.
I want to take advantage of the 2 dividers after the PLL output to generate pairs of frequencies…
Part Number: CDCE913 Hi team,
Could you help to double check whether TI clock pro can program the duty cycle or sync trigger edge singal?
For the selection of a clock generation IC chip, the requirements are as follows:
The working power supply is 3.3V…
Adarsh,
I would recommend for the CDCE913 either using a separate ferrite bead for VDDOUT or using the same ferrite bead for all VDD & VDDOUT, rather than keeping VDDOUT straight from the supply. I have re-assigned this to the proper team for the SN65DSI83…
Part Number: CDCE913 Dear team,
I knew we could recycle Vdd to set CDCE913's register to default value. May I know is there any other method to reset CDCE913 like reset by I2C command? Thank you.
Regards,
Polly Chung
Part Number: CDCE913-Q1 Hi team,
I have two question about the CDCE913-q1.
- According to datasheet, the spread spectrum can be set to each output. Is it possible to turn on or off the SSC each outputs?
- How much do we freely set the SSC width?
Thanks…
Part Number: CDCE913 Hi,
"Data Retention" is specified on the datasheet.
・Is counting started from writing?
・Is this specification condition Ta=85℃ and 100 programming cycle?
・Do you have reference data on different condition?
(My customer…
Part Number: CDCE913 Other Parts Discussed in Thread: CLOCKPRO Hi,
Does lock stability depend on PLL setting?
In detail, is lock stability deference on below settings?;
1. fin=27MHz, N:3120, M:507, Pdiv:5, fout=33.23MHz
2. fin=27MHz, N:80, M:13, Pdiv:5…
Part Number: CDCE913 Hi,
My customer is evaluating CDCE913 and uses not a Xtal but an external clock.
When the external clock stops and restart, PLL of CDCE913 does not lock.
What is recommended workaround for this condition?
Best Regards, Kuramochi