Part Number: CDCE937 Other Parts Discussed in Thread: CDCE949 , CDCE925 , CDCE913 I am using CDCE937 for a new design. I want to use this part to generate 6 frequencies total, 2 frequencies per PLL using the associated dividers. My questions are as follows…
Part Number: CDCE949 Other Parts Discussed in Thread: LMK04832 Hello,
Two CDCE949 are connected in parallel and are fed by the same input clock (20 MHz).
What is the maximum Skew between a signal from the first devide and a signal from the second?
Part Number: CDCE949-Q1 Hi,
In my design , CDCE949-Q1 input is a 25MHz cystal, the Y3 output is also 25MHz, which is used for Ethernet PHY. In datasheet, CDCE949-Q1 output clock jitter is Peak-to -Peak period jitter：
but the Ehternet PHY input clock…
Part Number: CDCE949-Q1 Clocking team,
I have a question regarding the CDCE949-Q1 clock synthesizers I2C bus specs.
1) How does the device determine if it is operating in Standard Mode or Fast Mode?
2) On page 5 of the datasheet (attached). The spec…
Part Number: CDCE949 Other Parts Discussed in Thread: CLOCKPRO Hi Sir
May we must connect to EVM when we use TI Clock pro?
Because we have no EVM on hand.
may you pls help use TI Clock pro set CDCE949 Y2 output 66MHz，then output TXTfile to us for reference…
Part Number: CDCE949 Other Parts Discussed in Thread: LMK00334-Q1 , LMK00804B , hi dear supporting team,
for CDCE949-Q1,LMK00334-Q1,LMK00804B, if there are unused CLKIN, oscin, how to handle it? should we float it or AC couple to GND? and how about the unused…
Part Number: CDCE949 Hello,
I would like to create 25 MHz PLL out and I have found two PLL settings:
- Input clock is 27 MHz.
- Y7 is my target PLL in the attache TI Clock Pro capture file.
1. first settings (2015_1223)
M = 486
N = 3600