• TIDA-010057: TIDA-010057 CDCE949 config file

  

  Bart Peeters

  TI Thinks Resolved

  Part Number: TIDA-010057 Other Parts Discussed in Thread: CDCE949 , CDCEL9XXPROGEVM , CLOCKPRO I am building a copy of the TIDA-010057 board since it is not for sale. The design guide (TIDUEP0–May 2020) states at page 20 that the config file of the CDCE949…

  • over 5 years ago
  • Simulation, hardware & system design tools
  • Simulation, hardware & system design tools forum

• CDCE949: CDCE949 set up question

  

  Chen Bogey8

  TI Thinks Resolved

  Part Number: CDCE949 Other Parts Discussed in Thread: CLOCKPRO Hi Sir May we must connect to EVM when we use TI Clock pro? Because we have no EVM on hand. may you pls help use TI Clock pro set CDCE949 Y2 output 66MHz，then output TXTfile to us for…

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE949-Q1: SCL hysteresis

  

  Atsushi Hirai

  Resolved

  Part Number: CDCE949-Q1 Hi team, My customer want to know the hysteresis value of I2C SCL input. Please support. Regards,

  • Resolved

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum

• CDCE949: Looking for explanation of the P Q R parameters

  

  Lee Fletcher

  Part Number: CDCE949 I am looking for explanation of the P Q R parameters for CDCE949. I can choose N & M parameters and I can calculate the P Q R parameters. Though not specifically stated, it seems that results with R = 0 may be be desired above R …

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE949-Q1: LVCMOS clock input mode

  

  Atsushi Hirai

  Resolved

  Part Number: CDCE949-Q1 Hi team, 1) Why the EVM has AC coupling(C4) at the clock input even though it's LVCMOS input? 2) For Xin/CLK-pin on the IBIS model, which XTAL input or LVCMOS input is modeled? My customer want to simulate with LVCMOS input…

  • Resolved

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum

• CDCE949-Q1: Ioz leakage current of 3-state output

  

  Atsushi Hirai

  Part Number: CDCE949-Q1 Hi team, Can we provide the evaluation result(min/max or ave+stdve) for leakage current on Yx-pin in 3-State output? Best Regards,

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE949-Q1: Crystal Spec

  

  Jerry Chu

  Resolved

  Part Number: CDCE949-Q1 Other Parts Discussed in Thread: CDCE949 Hi Expert, The crystal vendor said that the crystal stability is -90ppm, what's CDCE949 recommend? Or how to decide it? Thanks!

  • Resolved

  • over 7 years ago
  • Clock & timing
  • Clock & timing forum

• CDCE949-Q1: Create the various voltage and frequency

  

  Taito Takemura

  TI Thinks Resolved

  Part Number: CDCE949-Q1 I would like to create various clocks by clock generator. I guess this device CDCE949-Q1 is close to the correct as far as I searched. I would like the solution which can handle various clocks of voltage (1.0Vpp, 1.8Vpp and 3…

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE949: Which is better between the following two PLL settings in CDCE949?

  

  Jay Nam

  Resolved

  Part Number: CDCE949 Hello, I would like to create 25 MHz PLL out and I have found two PLL settings: - Input clock is 27 MHz. - Y7 is my target PLL in the attache TI Clock Pro capture file. 1. first settings (2015_1223) M = 486 N = 3600…

  • Resolved

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCE949-Q1: Start up time, Wait time for I2C ready

  

  Atsushi Hirai

  Resolved

  Part Number: CDCE949-Q1 Hi team, Could you check the start up time from VDD ramp(S0 pulled up to VDD) to Yx output? And, could you check the required wait time from VDD ramp to ready I2C access. Best Regards,

  • Resolved

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum

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