Part Number: CDCE949-Q1 Tool/software: I would like to use the IC in default mode (no I2C communication) with clock input of 600kHz and 9 outputs at 600kHz.
It seems feasible from my understanding of the default mode. The only thing that I'm not sure…
Part Number: CDCE949-Q1 I would like to create various clocks by clock generator. I guess this device CDCE949-Q1 is close to the correct as far as I searched.
I would like the solution which can handle various clocks of voltage (1.0Vpp, 1.8Vpp and 3…
Part Number: CDCE949-Q1 Hi team,
Can we provide the evaluation result(min/max or ave+stdve) for leakage current on Yx-pin in 3-State output?
Best Regards,
Part Number: CDCE949-Q1 Hi team,
1) Why the EVM has AC coupling(C4) at the clock input even though it's LVCMOS input?
2) For Xin/CLK-pin on the IBIS model, which XTAL input or LVCMOS input is modeled? My customer want to simulate with LVCMOS input…
Part Number: CDCE949-Q1 Hi team,
Could you check the start up time from VDD ramp(S0 pulled up to VDD) to Yx output?
And, could you check the required wait time from VDD ramp to ready I2C access.
Best Regards,
Part Number: CDCE949-Q1 Hi Team
There is a good new that DIN CDCE949QPWRQ1
1. Customer currently using CDCE949QPWRQ1 IC. If they need to set the Y4 POCLK configuration to 26.8MHz, what parameters do i2c need? THX
2. Please help check this SCH, …
Part Number: CDCE949-Q1 Hi,
In my design , CDCE949-Q1 input is a 25MHz cystal, the Y3 output is also 25MHz, which is used for Ethernet PHY. In datasheet, CDCE949-Q1 output clock jitter is Peak-to -Peak period jitter：
but the Ehternet PHY input clock…
Part Number: CDCE949-Q1 Clocking team,
I have a question regarding the CDCE949-Q1 clock synthesizers I2C bus specs.
1) How does the device determine if it is operating in Standard Mode or Fast Mode?
2) On page 5 of the datasheet (attached). The…
