• CDCI6214: Jitter of two-divided frequency.

  

  Shubiao Wang

  TI Thinks Resolved

  Part Number: CDCI6214 Hi there, customer requirement: input 52Mhz LVDS CLK, output 26Mhz LVDS CLK, is it achievable by CDCI6214? if yes, what's the expected jitter caused by CDCI6214? BRs, Shubiao

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCI6214EVM: CDCI6214

  

  Shams Syed

  Resolved

  Part Number: CDCI6214EVM Where can I find any information on how to use the Wizard to set target frequencies? There are are two many options in the Wizard

  • Resolved

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCI6214: questions about chX_cmos_pol and chX_outbuf_ctrl

  

  Kazuhiko Hirano

  Resolved

  Part Number: CDCI6214 Hello, My customer would like to output the same polarity LVCMOS signals at Y2P and Y2N. What values should be set for ch2_cmos_pol and ch2_outbuf_ctrl respectively? Best regards, K.Hirano

  • Resolved

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum

• CDCI6214: Related register setting for 100khz output

  

  Michael Jeong1

  TI Thinks Resolved

  Part Number: CDCI6214 Other Parts Discussed in Thread: CDCDB800 Hello Expert, Our customer want to know which register they have to set for 100khz output. Could you please give me example setting for this? Their target output is 100khz. Best regards…

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum

• CDCI6214: No clock signal on the output

  

  Peter Sveistrup

  TI Thinks Resolved

  Part Number: CDCI6214 I have a technical support question regarding your CDCI6214 chip. we are using this clock generator to redistribute a single ended 125MHz clock from a phy. We are using the REFP input for the 125MHz signal, as per the datasheet,…

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum

• CDCI6214: The range of VXIN

  

  Frank QIN

  TI Thinks Resolved

  Part Number: CDCI6214 Hi Team, According to the datasheet, I didn't found the requirements of VXIN when crystal mode. Is there any VXIN range? Also please provide a XIN pin's requirements of the voltage of Vhigh, Vlow, Vpp. Great thanks BR…

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCI6214: Registers

  

  Irmak Ece Sener Yalcin

  Resolved

  Part Number: CDCI6214 Hello, There are 55 registers described in the datasheet SNAS734E Table 15. However, Ticspro generates 70 register values. What are the descriptions of the non-described registers? Kind regards, Irmak

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCI6214: Questions about REFSEL, EEPROMSEL and RESETN/SYNC

  

  Kazuhiko Hirano

  Resolved

  Part Number: CDCI6214 Hello, My customer has a couple of questions as follows. Q1: When gpio0_input_sel = 0, without power cycle, REFSEL and EEPROMSEL can be resampled by toggling RESETN/SYNC (High to Low to High)? Q2: Without RESETN/SYNC toggling, is…

  • Resolved

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCI6214: CICI6214 Phase Jitter

  

  YEH ELVIS

  Resolved

  Part Number: CDCI6214 Hello, In our application. The ch1 is 50M AC-LVPECL, ch2 is 100M HCSL and ch3 is dual 25M LVCMOS. Input is 25M OSC. For 50M AC-LVPECL. The chipset input criterion is <1ps@12k~20M, But our measure result around 1.5ps. Can we…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• CDCI6214: zero delay mode

  

  Moshe Lerner

  Part Number: CDCI6214 Hello. I need to run the CDCI6214 as zerodely buffer. The input is 100MHz, differential HCSL type connected to REF input. The outpus shall be as following - Y1, 100MHz HCSL type - Y4, 100MHz HCSL type The I2C interface of CDCI is…

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

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