Part Number: CDCLVC1102 HI,
Attached my design for review,
I need to give 24MHZ clock to RSCLK pin of DSP and BITCLK of CODEC, Will this design work as is?
Part Number: CDCLVC1102 The CDCLVC1102 datasheet only shows the power consumption characteristics (Pdyn & Pcload) for the 2.5V supply in Figure 1.
What are the power consumption characteristics for a 3.3Vdc supply?
Part Number: CDCLVC1102 Other Parts Discussed in Thread: LMK1C1102 HI!
I need a Buffer to fan out 1PPS signal of LVTTL_3.3 standard without degrading the accuracy.
Can CDCLVC1102 buffer be used for such purpose?
does it support Duty cycle adjustment …
Part Number: CDCLVC1102 Hi There,
We are planning to interface HCMOS output of OCXO clock oscillator to CLKIN of CDCLVC1102 LVCMOS buffer chip. Can we do this?
HCMOS output logic level is 90% VDD (it is 2.97V as we operate at 3.3V power) and VOL (max…
Part Number: CDCLVC1102 Other Parts Discussed in Thread: LMK1C1102 Dear team,
I found VDD specification like below at datasheet. This device is recommended using 2.5V or 3.3V supply.
But, How about 2.8V VDD? Is this value is not available? Please let…
Part Number: CDCLVC1102 Hi support team,
When the 1G pin changes from Low to High when the CLKIN input is High, is a short pulse output from the Yx output? It is explained that the 1G pin is asynchronous.
Is the LMK1C110x possible to prevent the generation…
Part Number: CDCLVC1102 My customer has a question,
When VDD is configured to 2.5v, do the inputs signals tolerate 3.3v.
P.S. I don't think so as then Vin > VDD+0.5V as mentioned in Abs Max ratings. Please confirm.
Part Number: CDCLVC1102 Hi
We are designing a PTS(Product testing System) where some High frequency 208MHz clock is used in DUT device and here we have to check its frequency through some POGO pins, then came to our board then go through cable connector…
Part Number: CDCLVC1102 Wondering if you can handle .8-.9 nsec/V min slew rate - for a 160 MHz clock signal coming from ABLJO-160MHz device.
Says output rise and fall time can be 4 nanoseconds worst case.