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  • RE: CDCLVC1310: external pull up/down resistor for single ended input connection

    Resolved
    Hi Megha, To input a LVCMOS clock to CDCLVC1310, (1) All modes could accept the single end LVCMOS input. Considering performance, 00 and 01 is preferred. 00 PRI_IN: DC couple. Refer to below Figure 3, but 100 ohm pull-up/pull-down resistors are…
    • Answered

  • CDCLVC1310: external pull down/up resistor of PRI and SEC pin

    Resolved
    Part Number: CDCLVC1310 Hi team, For unused input pin, If we can just let PRI_INN/P and SEC_INN/P pin floating, or the external Pull up/down resistor is necessary ? Thank you.
    • Resolved

  • CDCLVC1310: Output skew when device is working @30MHz single-ended input and 25%/75% duty cycle

    TI Thinks Resolved
    Part Number: CDCLVC1310 Hi, team, My customer has one question about CDCLVC1310. They have one application that the clock is 30Mhz single-ended, and the duty cycle is 25%, 50% and 75%. Is there any result about the maximum output skew under 25…
    • Answered

  • CDCLVC1310 thermal pad connection

    Resolved
    Should I connect thermal pad to ground or not?
    • Resolved
    • Answered

  • RE: CDCLVC1310: XIN, PRI_INP, SEC_INP all three are connected to three different input lines but can it be of same type such as LVCMOS

    Resolved
    Hi Megha Xin pin in bypass mode supports single ended input. So to answer your question, yes, three inputs can be of type LVCMOS . Best regards Puneet “ If this answered your question, please click “ This Resolved My Issue ” button.

  • CDCLVC1310: The output phase change when switch between same phase source PRI and SEC clock input

    TI Thinks Resolved
    Part Number: CDCLVC1310 Hi Team, There is a question from the customer for CDCLVC1310. If the PRI and SEC are phase aligned,will the output clock phase change when switch the source between PRI and SEC? Best Regards, Nick Dai
    • Answered

  • CDCLVC1310 unused pins

    Resolved
    Other Parts Discussed in Thread: CDCLVC1310 Hi, On the CDCLVC1310, 1. If XTAL input is not used, what should be with the XIN and XOUT pins? I suspect the answer is to tie XIN low and leave XOUT unconnected. 2. If driving PRI_INP and SEC_INP with…
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    • Answered

  • CDCLVC1310 - System-level additive jitter @25MHz

    Resolved
    Other Parts Discussed in Thread: CDCLVC1310 Hello, My customer has a request about CDCLVC1310. [Request] Do you have the data of system-level additive jitter in fin/out = 25MHz ? Best Regards, Hiroshi Katsunaga
    • Resolved

  • CDCLVC1310 TCXO Clipped Sinewave support

    Other Parts Discussed in Thread: CDCLVC1310 Hi, I am using CDCLVC1310 clock buffer in our design and would like to check if we can use a TCXO with clipped sinewave output on CDCLVC1310's Differential/ LVCMOS clock inputs by ac-coupling and providing…

  • CDCLVC1310 - Input Termination

    TI Thinks Resolved
    Other Parts Discussed in Thread: CDCLVC1310 Hi, Please help us on the CDCLVC1310 input temination. Our customer connects FPGA CMOS output to CDCLVC1310 input. [Question] Do you must use Thevenin termination at the input of CDCLVC1310 ? I am asking…

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