Answered

• CDCLVP1102: CDCLVP1102 to Artix ultrascale+ LVDS input

  

  Hamed Sotoudi Namin

  Resolved

  Part Number: CDCLVP1102 Dear Sir/Madam, in our project we used CDCLVP1102 as input trigger interface to the FPGA. As the chip is LVPCEL it is powered with 3.3V and the FPGA bank is powered with 1.8v. According the FPGA documents , the LVDS IVDiff is…

  • Resolved

  • 9 days ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Frequency for CDCLVP1102

  

  Syed Rahman

  TI Thinks Resolved

  Part Number: CDCLVP1102 Tool/software: Hi, I am planning to use CDCLVP1102 in my design. Datasheet shows it works at 2GHz. Our designed frequency is 122.8MHz. Will it work at this frequency. Thanks, Syed

  • 9 months ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Consultation on LEPECL Interface Design

  

  Aaron

  Part Number: CDCLVP1102 Dear TI Engineer, We are using the CDCLVP1102 to convert a 3.3 V, 10 MHz clock signal into an LVPECL signal, which is then fed into a clock device. In the application report SCAA056 , the calculation methods for the termination…

  • 1 month ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Package orientation

  

  Parameswaran Sakthivel

  TI Thinks Resolved

  Part Number: CDCLVP1102 Tool/software: Hi According to the datasheet, the orientation of the MPN CDCLVP1102RGTR indicates that pin 1 is located at Q2. However, we require pin 1 to be positioned at Q1. Could you please confirm if this option is avai…

  • 7 months ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: Single-end clock input

  

  Kei Kuwahara

  Resolved

  Part Number: CDCLVP1102 Tool/software: Hello team, My customer would like input AC-coupled single-end clock to this device. (They can't use DC coupled) How should I configure the input to CDCLVP1102? I am thinking as figure below. Could you please…

  • Resolved

  • 11 months ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: Differential Input Voltage Specification

  

  Gary Stein

  Resolved

  Part Number: CDCLVP1102 Other Parts Discussed in Thread: LMK1D1208 Tool/software: The CDCLVP1102 datasheet lists maximum Differential input peak-peak voltage as 1.5V. Figure 14 shows a DC-coupled LVCMOS as an input to INP, with INN biased to 1/2 of…

  • Resolved

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCLVP1102: Recommended Design for CDCLVP1102

  

  Guohai Lin

  Resolved

  Part Number: CDCLVP1102 Hi Teams， Happy new year for 2024！ My customer is considering CDCLVP1102 and has some questions need to answer: 1. Can you provide the recommended application schematic diagram? 2.Customers need two outputs to reach the…

  • Resolved

  • over 2 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: Does this fanout buffer require any specific Duty cycle

  

  Nathan Baltz

  TI Thinks Resolved

  Part Number: CDCLVP1102 Tool/software: Hi, Does the CDCLVP1102 require any duty cycle for the input? Can it be used for example for PPS (Pulse Per Second) applications where the duty cycle might typically be like 0.002%. Thanks,

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: The actual input capacitance of cdclvp1102

  

  Charlie Xiao

  TI Thinks Resolved

  Part Number: CDCLVP1102 Hi, The c_comp of the differential input of the IBIS model is 0.3pF, but the Icap input in the datesheet is 5pF, Δv/ΔT=1.5v/ns, both of which describe the input capacitance of the transistor. Why is there such a big difference…

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum

• CDCLVP1102: What is the propagation delay temperature coefficient of this part

  

  Nathan Baltz

  TI Thinks Resolved

  Part Number: CDCLVP1102 Tool/software: Hi, Does anyone have the temperature coefficient of propagation delay for this differential PECL input dual differential PECL output part? Nathan

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum

Didn't find what you are looking for? Post a new question.