Part Number: CDCLVP1204 Tool/software: Hello,
I'm updating a design and I want to connect an unused output from CDCLVP1204 (Vcc = 3.3 V) to a differential clock input on an Altera Agilex 7 FPGA in a 1.2 V bank. It is a 50 MHz clock.
Figure from: Agilex…
Part Number: CDCLVP1204 Tool/software: dears,
my customer set the pull up and pull down resistor as recommended, but the max LVPECL Differential voltage input voltage will be about 1.8~2V, the device output signal is normal.
will the over spec differential…
Part Number: CDCLVP1204 Tool/software: Hello
I have a thermal issue with CDCLVP 1204
Can you send me a graph of MTBF Vs temp for this component?
Best regards
Shay
Part Number: CDCLVP1204 Tool/software:
Dear
For the parts,CDCLVP1204RGTR, we found the DC on marking is 2340+(3A) while DC on labei is 2338+(39) and 2347+(3B); pls see the picture, they are mismatched.
is it normal?
The lot code is 3896635T43
Part Number: ADC34J24 Other Parts Discussed in Thread: CDCLVP1204 , LMH3401 , LMH5401 I am looking to drive the ADC34J24 with a CDCLVP1204 as I need to distribute the SYNC to multiple ADC's.
The CDCLVP1204 has LVPECL output but the ADC34J24 requires…
Part Number: CDCLVP1204 Other Parts Discussed in Thread: CDCLVD1204 , LMK1D1204 Hi Team,
Customer wants our double check for their clock design, 05318B (LVDS) -> CDCLVP1204 (LVPECL) ->PHY (LVDS). If it looks ok to do so?
The main reason to use CDCLVP1204…
Part Number: CDCLVP1204 Hi,
Our customer wants to know the VIH/VIL value of the IN_SEL pin. Is this the performance of the D/S LVCMOS Input?
Best regards,
Hiroshi
Part Number: CDCLVP1204 Hello Team,
can you provide the switching time when using IN_SEL to gate a 2MHz clock at IN0 while setting IN1=0, please? This timing is not specified in the data sheet.
Also, will the switching be glitch free?
Thank you…
Part Number: CDCLVP1204 Hi,
I'm sorry. Tell me again about IN_SEL's Vih/ViL.
Checking the specifications of the LVCMOS input, it is an external threshold voltage applied to complementary input. On the other hand, IN_SEL is a single-ended input, so…