Part Number: CDCM1802 Hi team,
My customer has some questions and please help to advise.
Thanks
Maximum input level of RF (differential mode)?
RF Output level (differential mode)?
Is RF Output level programmable?
Part Number: CDCM1802 Tool/software: HI TI
We are designing a clk divider solution , Detailed requirment is to divide LVCMOS18 76.8MHZ (single input)refclk into LVCMOS18 38.4MHZ (low additive j itter <500fs )(single output) ;
Whether LVCMOS18 can…
Part Number: AFE58JD48EVM Other Parts Discussed in Thread: CDCM1802 , , LMK04826 Tool/software: Hi,
I would like to understand the clock tree of the AFE58JD48EVM : What is the role of the CDCM1802 component?
The JESD interface between the FPGA and…
Part Number: CDCM1802 Hi,
We are using this part for LVCMOS Input and LVCMOS output function where the output of Y1 is used. The Differential LVPECL output on Y0 / Y0_N is left floating. To disable the LVPECL function, we intend to GND pins VDD0 &VDD0_1…
Part Number: CDCM1802 Dear Team,
My customer would like to find a single-ended clock buffer.
They hope it could drive 3MHz digital clock with 22 ohm + 62pF loading.
Does CDCM1802 have enough driving capability to make it work? If not, do we have…
Part Number: CDCM1802 Hi Team,
My customer would like to use CDCM1802 for their 100M Hz clock signal.
May I know what is the maximum trace length that CDCM1802 can drive?
Thank you.