Part Number: CDCM6208 Does the CDCM6208 require configuration over I2C on every power up? Or is there a way to store user configuration over I2C in non-volatile memory?
Part Number: CDCM6208 Hello,
Which are the differences between CDCE6208V1 and CDCM6208V1F?
On the other hand, is it necessary to sypply the not used outputs? Is it necessary to add external components in not used outputs?
About the power supply for VCO…
Part Number: CDCM6208 Hello TI-support team,
we are using the CDCM620V2 and have a strange behavior with I2C communication.
Means that the CDCM6208 doesn't send an ackknowledge with the first try of read_id after power up in one of our products.
…
Part Number: CDCM6208 Other Parts Discussed in Thread: CDCE6214 , , LMK03318 Hello,
My customer is looking for a low cost clock solution that can receive 30.72MHz TCXO output and multiply it by 2/4 to output 61.44MHz/122.88MHz as below.
- Input : TCXO…
Mike,
As is discussed in this thread, it will be substantial effort to get one of the designers to run this simulation over a wide array of cases: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/833612/lmk03318-propagation…
Part Number: CDCM6208 Hello,
I am simulating a clock generator using CDCM6208 with TICs Pro Tool.
Please find a block diagram below:
Now, I want to design the loop filter but to compare different phase noise is necessary to include the reference clock…
Part Number: CDCM6208V2EVM Hi,
Is there a BOM for this EVM too?
Also interested in the project file instead of gerber itself, if you have it, the gerber file is very hard to understand and there is no schematics that matches the gerber!
Regards
Part Number: CDCM6208 Hi,
The random jitter given in the CDCM6208 chip manual is only 0.3-0.625ps, while the total fractional jitter is 50ps-220ps. Random jitter and total jitter are not of the same order of magnitude (total jitter TJ >> random jitter…
Part Number: CDCM6208 Other Parts Discussed in Thread: LMK03318 , CDCE6214 , LMK03328 Dear Team,
Do we have any clock gen can meet the spec as below?
one switching two
two-way
support PCIe CLK: 100M
Many Thanks,
Jimmy
Part Number: CDCM6208 We use only secondary input for xtal input and VDD_PRI_REF is left open, and PLL is not locked.
Do we have to connect VDD_PRE_REF to VDD if we don't use the primary clock input?