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The CDCP1803RTH is now obsolete. It is replaced by the RGE package.
What is the reason for the replacement?
The RTH package was assembled by a subcontractor and RGE package is assembled by a TI assambly site.
Do I have to change something in my…
Other Parts Discussed in Thread: CDCP1803 Bonnie,
I got word that the model is working and they are evaluating it further…but is seems to be working and they are happy for now. Thanks for you help on this.
Best regards,
Shawn
…
Hi SM,
1. CDCP1803 buffer is used to divide OSTR output frequency from CDCE62005 by 2. This is needed when interpolation factor 16 is used.
OSTR input of DAC3484 needs to f_DAC_CLK / (8 * interpolation factor* n). For DAC interpolation 16, OSTR output should…
Part Number: DAC3162EVM Other Parts Discussed in Thread: CDCP1803 , SN65LVDS100 , DAC3162 Dear All,
I have the DAC3162EVM and the Xilinx AC701 (Xilinx Artix7 FPGA Eval Board).
The FMC connector on the DAC3162EVM and the AC701 are perfectly compatible. So…
Hi David,
Please follow the recommendations on Figure 11, Page 14 shown in the datasheet at the link below (this single-ended termination scheme also applies to CDCM7005). Note that this scheme applies only if Single-ended LVCMOS signals are driving the…
Other Parts Discussed in Thread: DAC3162EVM , DAC3162 , CDCP1803 , DAC3164 I'm using a DAC3162EVM in stock configuration (so, transformers enabled) and a TSW1400 board to control it. I am using the latest HSDC GUI (4.20). No matter what I do, I can't…
Other Parts Discussed in Thread: DAC3152 , CDCP1803 Hi,
Now i connect the DAC3152 to TSW1400,There is a clock generate by CDCP1803,and it used as FPGA_CLK that send to TSW1400,For example if the DAC3152 input
clock is 20MHZ,the output of FPGA_CLK is5…
Other Parts Discussed in Thread: CDCP1803 , DAC3162 Hi,
I am working on a project where the DAC3i62EVM is connected to the FMC connector on a Spartan6 SP601 Evaluation board. We are generating a gaussian wave for RF pulse shaping in a high power amplifier…
Hi Satoshi,
If you want to get a 80MHz differential clock output from a 640MHz clock input, I suggest use clock buffer instead of PLL synthesizer.
For example, LMK01000, LMK01010, LMK01020, CDCE18005, CDCM1802, CECM1804, CDCP1803. These clock buffers…
