Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.
Part Number: CDCS504-Q1 Other Parts Discussed in Thread: TAS6424 How is the timing delay of CDCS504-Q1?
Regarding the digital audio clock, I will use the 6.144MHz clock and put CDCS504-Q1 on where much closer to TAS6424.
So I will use CDCS504-Q1 as multiplier…
Part Number: CDCS504-Q1 Hi all Would you mind if we ask CDCS504-Q1? The datasheet shows Cycle-to-Cycle jitter only. Do you have the data of peak to peak jitter(Period Jitter)? Kind regards, Hirotaka Matsumoto
Part Number: CDCS504-Q1 Hi Team,
I have a question about CDCS504-Q1 input jitter tolerance performance.
CDCS504-Q1 datasheet describes output cycle to cycle jitter but no input jitter tolerance.
Could you let me know CDCS504-Q1 input Jitter tolerance…
Part Number: CDCS503 Other Parts Discussed in Thread: CDCS504-Q1 Hello,
I'm comparing CDCS503 vs CDCS504Q1, specifically looking at cycle to cycle jitter. The 503 is spec'd at 110ps at 108MHz, and the 504 is 144ps at 11.264MHz. Because of the different…
Chase,
This is a schematic for a TAS6422E-Q1 device. It is correct, but needs a MCLK.
The TAS6424 and TAS6422 family of devices needs a MCLK. The clock can be generated by the CDCS504-Q1. CDCS504-Q1 data sheet, product information and support | TI.com …
Hello, Arash,
Thank you very much for your support. Customer will try the method that I posted using CDCS504-Q1.
As a backup plan, they will also try a high-speed DAC like DAC121S101QCMKX/NOPB.
Best, Masaru