Part Number: CDCUN1208LP Team,
I'm having issues with CDCUN1208LPRHBT.....Sometimes it works sometimes it doesn't....
I've observed that input LVCMOS above VDD...is the device sensitive to that?
My 3.3 V comes up before the 1.8 V. Is that ok…
Part Number: CDCUN1208LP I would like to check if I understood the data seet right.
My use case is as follows:
I- LVDS input (IN1P and IN1N);
II- 8 LVDS outputs
III- VDD and VDDOx = 1.8V
IVa - Input frequency 5MHz, square
IVb - Input frequency 160MHz…
Part Number: CDCUN1208LP The data sheet informs the propagation delay (3.8ns max. @ 1.8V) for ERC set to high rate mode.
What would be the figures for medium and slow ERC settings? We set ERC to medium in our design (just in case measure for EMC).
…
Part Number: CDCUN1208LP Hello,
A customer was asking about the drive strength of the CDCUN1208LP part. I looked in the datasheet, and couldn't find it specifically discussed anywhere. Is there any information about the drive strength of this part I could…
Part Number: CDCUN1208LP Hello Team,
we are facing some challenges during the SPI communication with the device.
Things are looking now working, but out of the datasheet there are gray area:
in our first attempt we implemented the SPI write as it is shown…
Part Number: CDCUN1208LP I'm using CDCUN1208LP in PINS mode configuration. The input LVCMOS from a clock generator ABLJO-120 at 120 MHz is direct connected with input (lvcmos) The device seems work fine, but if I turn off my board and then turn on it…
Part Number: CDCUN1208LP Hello Team,
we are currently supporting a new FPGA code that would need to be trimmed to properly interface with the CDCUN1208.
For that design it would be handy to have some additional information for the following parameters…
Part Number: CDCUN1208LP
I have an issue with the CDCUN1208LP when trying to power up. The configuration is as follows:
3.3V powers the core (pin5) and VDDO4 (pin27)
1.8V powers VDDO1 (pin11) and VDDO2 (pin14)
VDDO3 (pin22) is floating with a 100nF…
Part Number: CDCUN1208LP I'm using this clock buffer for RF communication application and i want to make sure that is will not insert too much of phase noise to clock entered to the RFIC
Thanks
