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Part Number: CDCVF25081 Hi All,
I have a question about CDCVF25081.
Customer is using Renesas 2308B and is considering to change to CDCVF25081.
The 2308B can adjust the skew with the FBK terminal, but I don't think the CDCVF25081 can adjust the skew.…
Part Number: CDCVF25081 We need a zero delay buffer in the clock path normally. However the zero delay buffers have a min frequency requirement that doesn’t work out for JTAG testing.
I noticed that this part when the S2 pin is a 1 and the S1 pin…
Part Number: CDCVF25081CDCVF25081 PLL drivers's datasheet says
"Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be wired to one of the outputs to complete the feedback loop of the internal PLL "
But the problem…
Part Number: CDCVF25081 Hi guys.
I'm looking for a high multiplication solution for PLL.
Would the CDCVF25081 be a good choice for a ~800,000X frequency multiplier PLL @ output ~50MHz ?
The output Freq. is in the range i'm looking for, and i'm wondering…
Hi,
I would like to ask you a question about the specification of "Cycle-To-cycle jitter vs Frequency"?
There describes the specification on datasheet page8, fig 6.
Is this spec applied to only "PLL mode" or both "PLL mode" and "Non PLL mode…
Other Parts Discussed in Thread: CDCVF25081 Hi,
I would like to ask you 2 questions about CDCVF25081 16pin connection.
Q1) Must 16pin be connected one of 8 outputs (1Y0 - 1Y3, 2Y0 - 2Y3)?
If yes, for example, 1Y3(15pin) is very useful to connect due to…
Other Parts Discussed in Thread: CDCVF25081 , CDCVF2509 Hi,
My cutomer is planntin to use IDT2309.
So I would like to propose CDCVF25081 to the customer against IDT2309.
Because CDCVF25081 seems to be "pin-compatible" with IDT2309 without "pin16".…
Other Parts Discussed in Thread: CDCVF25081 Please let me know about the operation on the output side when CLKIN of CDCVF25081 disconnect suddenly.
Example
・After it is behind for a while (A few ms), turn off.
⇒After CLKIN turns off, how many "continueous…
Hithesh,
In the IBIS file of this model the CDCVF25081_OUT is modeled. This output buffer is captured under the [Model Selector] section at the beginning of the file on line 88. In this statement, the buffer behavior of CDCVF25081_OUT is split into two…
