Answered

• CDCVF855: FBIN and FBOUT

  

  Takashi Yamaguchi

  Resolved

  Part Number: CDCVF855 Hi team, My customer is considering to use the CDCVF855. Could you please advise me on the question below? How should I handle the FBIN and FBOUT pins? Should FBOUT be looped back to FBIN? If there is a recommended circuit, please…

  • Resolved

  • over 4 years ago
  • Clock & timing
  • Clock & timing forum

• CDCVF855: ESD

  

  Amy Luo

  TI Thinks Resolved

  Part Number: CDCVF855 Hi team， My customer needs to know the ESD parameter when using CDCVF855PW, which is not given in the datasheet. Could you help to provide the parameter value. Thank you. Best Regards, Amy Luo

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCVF855: 1 to 2 zero zero-delay buffer

  

  Di Wang

  Resolved

  Part Number: CDCVF855 Other Parts Discussed in Thread: CDCI6214 Hi, I need a 1-to-2 zero zero-delay buffer. The clock is 125MHz LVDS, and LVPECL is also accepted. I'm looking at CDCVF855. Could you show me any reference schematics? I would like to refer…

  • Resolved

  • over 8 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCVF855 / IBIS model

  

  Toshiyuki

  Resolved

  Other Parts Discussed in Thread: CDCVF855 , CDCVF857 Hi, Could you provide us IBIS model of CDCVF855 ? A lternatively, could we use CDCV857 model ? In addition, Is the FBOUT specification same as Yx outputs? Best Regards, Kato

  • Resolved

  • over 10 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• Phase offset of CDCVF855

  

  g.f.

  Resolved

  Other Parts Discussed in Thread: CDCVF855 Hi, I have questions about CDCVF855. Q1. In CDCVF855 datasheet page.6, there are value of "static phase offset" as +/-50ps. Is this "phase offset" means that variation in CLK and FBIN is within +/-50ps? …

  • Resolved

  • over 11 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• CDCVF855 Dynamic Data

  

  cafain

  Resolved

  Other Parts Discussed in Thread: CDCVF855 , CDCV855 , CDCVF857 Hi Please ask questions. There is a description of the following items in the data sheet of CDCV855, but it is not is written in CDCVF855. 1.td(0) Dynamic Pahse offset (this includes…

  • Resolved

  • over 11 years ago
  • Clock & timing
  • Clock & timing forum

• CDCVF855 SSTL-2 buffer clock o PLL

  

  Elena Faventi

  Other Parts Discussed in Thread: CDCVF855 Hi, I was thinking about to use CDCVF855PW to generate two SSTL-2 clock for a JEDEC 266 DDR. I start by saying that I've never used before a SSTL-2 buffer and that I'm not so much expert in differential standards…

  • over 12 years ago
  • Clock & timing
  • Clock & timing forum

• RE: LMK00804B-Q1: How to design the delay time?

  

  Lane Boyd

  Hi Anne, Sorry for the delay. It seems that the 1.8ns delay between the outputs is required, which will be used to drive both the receiver and sender. Unfortunately it is not possible to set the delay between outputs using LMK00804B-Q1. You might…

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• Zero delay clock multiplier with 2.5V, single end input/output

  

  Kawai

  Resolved

  Other Parts Discussed in Thread: CDCVF25081 , CDCVF855 , CDCE62002 Hello Team, Our customer is looking for a zero delay clock multiplier which could be used with 2.5V. Is there a 2.5V version device of CDCVF25081 ? I could find some zero delay clock…

  • Resolved

  • over 11 years ago
  • Clock & timing
  • Clock & timing forum

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