Part Number: DAC3171 How should the "tempdata" field of SPI Register config6, bits 15:8 be interpreted?
Is this degrees celsius? whole or fractional degrees? Signed or unsigned?
I have an additional question:
The datasheet for DAC3171 does not appear to specify setup and hold timing for the align signal. From the app note you attached there are similar DACs that do have this specified, both are equivalent with 0 ps for setup…
Other Parts Discussed in Thread: DAC3171 I've been struggling for the past week with an issue where I've been attempting to get a DAC3171 working in DDR mode with an Artix 7 FPGA. The DAC appears to be rejecting the lower 7 bits. While going through…
Hi,
We recently put a new revision of the DAC3171 on the web dated January 2016. It tries to make clear the relationship between the four delay fields and the input signals they affect. The block diagram figures 66 -69 include text to indicate which delay…
Other Parts Discussed in Thread: CDCE62002 , DAC3171 I'm a bit lost defining what register should be written and their value. My application uses a DAC3171 with 14 bit interface. A CDCE62002 generates the PECL DACCLK to the DAC3171 and a LVDS clock to an…
Hello,
As you suggested, I set the bit D13 of Address 0x1 to 0: (When asserted the input interface is changed to use the full 14-bits for each word, instead of dual 8-bit buses for two half words).
But The result is not changed.
In my original Setting…
Other Parts Discussed in Thread: DAC3171 Hi!
I`m again fighting against a DAC3171 to configure it
Signals come from a FPGA, who works as a multiplexer of the SPI signals generated by a K60 Kinetis Cortex CPU.
In a past post you suggest me to check first…
Felix,
For the ADC, take a look at the ADS54J66, ADS54J54, ADS58J63 or the ADC12QJ800.
For the DAC, take a look at the DAC3161 or DAC3171.
Regards,
Jim
Part Number: CDCE62005 Other Parts Discussed in Thread: DAC3171 , LMK01801 Hi Team!
My customer is interested in using DAC3171 to convert digitized ultrasound data to an analog output.
They want to use a 400MHz LVDS clock from FPGA to drive the DACCLK LVPECL…
