Part Number: DP83620 Tool/software: In RMII master mode (w/ CLK_OUT_EN = HIGH), how does the CLK_OUT (RX_OUT, TX_OUT) Clock Ref output signals behave when then the DP83620 is in Reset (i.e. N_RESET = LOW).
During the DP83620.Reset = LOW event, are the…
Part Number: DP83620 This was previously entered on Case CS3347519 and escalation number ESC0030425.
Customer identified that this part on the boards listed above has a pin that is pulling a signal down that it should not be pulling. When the component…
Part Number: DP83620 Looks good. Here is a tweaked version:
We are noticing peculiar behavior on the TXD_1, pin 4 on one batch of DP83620. Approximately 10% of the parts are experiencing this behavior.
Date code: 37AT6TUG3
The issue is with power…
Part Number: DP83620 Tool/software: Hi team,
Can the 49.9Ω in Figure 9-1 be changed to another resistance value? I am concerned that 49.9Ω would consume too much VDD.
Best Regards, Ryu.
Part Number: AM6422 Other Parts Discussed in Thread: DP83620 Tool/software: Hello,
We use the hardware we developed ourselves to ping the problem when using ICSSG0's emac0. The PHY chip used is DP83620 and the interface is MII. Currently, network connections…
Part Number: AM6422 Other Parts Discussed in Thread: DP83620 , , SYSCONFIG Tool/software: Hello!
I use the AM6422 CPU and the DP83620 chip to connect to the ICSSG Ethernet in RTOS. Use MII mode,there is currently no corresponding PHY driver,Can you…
Part Number: DP83620 Tool/software: Hello!
We are using the AM64 development board RTOS system. The current hardware Ethernet PHY model is DP83620. Can you provide the driver source code of DP83620 and the operation instructions for adding PHY driver…
Part Number: DP83620 Background:
I have a DP83620 with the FX_EN_Z input strapped low for operating in 100BASE-FX mode.
The PHY is connected to an optical transceiver.
For normal operations, all works as expected with no problems.
Observed…
Part Number: DP83620
Hi Experts,
In our Project, we are using DP83620SQE/NOPB Ethernet Transceiver (RMII mode). During DVT Testing of Ethernet section, We have identified failure in MDC to MDIO (output) Delay Time with respect to Datasheet…