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Showing 207 results View by: Thread Post Sort by
  • DP83630: USE PHY as sniffer

    john young
    john young
    TI Thinks Resolved
    Part Number: DP83630 Question. I plan on using the DP83630 PHY with the TMS5704357BZWTQQ1 hercules uP (similiar to the setup on the HERC launchpad). Can I use the PHY as just a "sniffer" on an ethernet switch? that is, our customer does not want…
    • over 4 years ago
    • Interface
    • Interface forum
  • DP83630: Absolute max voltage rating

    Mark Philip Felipe
    Mark Philip Felipe
    Part Number: DP83630 Hi Team, Is there an absolute max voltage rating for the Ethernet port RX/TX function? Thank you. -Mark
    • over 4 years ago
    • Interface
    • Interface forum
  • DP83640: design a PCB compatible for both DP83630 (48-pin WQFN) and DP83640 (48-pin LQFP)?

    AnBer
    AnBer
    TI Thinks Resolved
    Part Number: DP83640 Other Parts Discussed in Thread: DP83630 Team, From you experience is it possible to design a PCB for both package? (in order to solder the one IC you can source at this point of time) DP83640: 48-pin LQFP Package (7 mm × 7 mm)…
    • over 3 years ago
    • Interface
    • Interface forum
  • RE: DP83630: DP83630 PTP improvement on stability

    Ross Pimentel
    Ross Pimentel
    Hi Leo, You can use the PGA or FCO within the DP83630. Please reference this application note: www.ti.com/.../snla099d.pdf Also, you can change the 1588 clock source using register 0x1B.
    • over 6 years ago
    • Interface
    • Interface forum
  • Answered
  • DP83630: DP83630_TPI Network Circuit

    Vladimir Naumenkov
    Vladimir Naumenkov
    Resolved
    Part Number: DP83630 Dear Sir, please, answer There is TPI Network Circuit on the figure 9-1 on the page 68 of the datasheet. Please, report, what power dissipation I can use for 49,9 Ohm resistors? ( let's take the case of the maximum possible…
    • Resolved
    • over 5 years ago
    • Interface
    • Interface forum
  • Answered
  • RE: DP83630: DP83630: Basic questions about DP83630 and IEEE 1588. (Part 2)

    Geet Modi
    Geet Modi
    Resolved
    Hi Kawai-san, My understanding is that PPS is always aligned with IEEE1588 clock-output. However if software correction is not done to IEEE 1588 clock-output, it will not be fully Synchronised to Master clock hence the 1 PPS. Regards, Geet
    • over 7 years ago
    • Interface
    • Interface forum
  • DP83630: False Carrier Sense Error and Receive Error Latch

    Saravanakumar S93
    Saravanakumar S93
    Part Number: DP83630 Other Parts Discussed in Thread: HALCOGEN Hi All, Currently, we are trying for the TI example program using Launchpad XL2 RM57 <=> Launchpad XL2 RM57. This board consists of DP83630 Ethernet PHY Transceiver IC. We are able to establish…
    • over 4 years ago
    • Interface
    • Interface forum
  • RE: Linux/DP83630: AM3359 DP83630

    Rob Rodrigues
    Rob Rodrigues
    Hi VLeshka, This appears to be an SDK issue if it works in SDK 3 and not SDK 5. I will move your thread to the Sitara for better visibility for the experts. Best Regards,
    • over 7 years ago
    • Processors
    • Processors forum
  • RE: DP83630: Guidance on PTP Implementation

    Geet Modi
    Geet Modi
    Hi, DP83630 as Master needs a reference clock to which it can run the Time Stamping enginer and generate the Time sync Packets. It can take 1 pps GPS signal and local 25 MHz and synchronise the Time Stamp engine or a 25 Mhz Synchronised clock. From…
    • over 5 years ago
    • Interface
    • Interface forum
  • Answered
  • DP83630: An invalid checksum generated with SYNC_1STEP

    Richard Hibbert
    Richard Hibbert
    Resolved
    Part Number: DP83630 Other Parts Discussed in Thread: DP83640 , I'm having a similar issue to that raised on the DP83640 but with the DP83630 namely "an invalid checksum generated with SYNC_1STEP". On the PTP_TXCFG0 register I have the following bits…
    • Resolved
    • over 4 years ago
    • Interface
    • Interface forum
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