Part Number: DP83TG721S-Q1 Tool/software: Hello all,
quick question: If I set a PHY into respective Ethernet compliance testmode 1 to 6 (lets take 6 for voltage droop as example)
what does the RGMII communication with the MAC do?
Does is go on as before…
Part Number: DP83TG721S-Q1 Tool/software: The data manual for the DP83TG721S-Q1 chip is incomplete, and information such as pin descriptions is not included. Can you provide a complete version of the data manual?
Part Number: DRA829V-Q1 Other Parts Discussed in Thread: DRA829 Tool/software: Hi expert,
Our customer is using DRA829 SGMII connecting to PHY DP83TG721-Q1. The SGMII eye width of Jacinto is 5pS. But the PHY need 200pS. Could you please check the huge…
Hi Xu,
This is for a different device, the DP83TG721: https://www.ti.com/product/DP83TG721S-Q1
You can find more information about this device if you have NDA with us, but we cannot share exactly what 0x55D does.
Best regards,
Melissa
Part Number: DP83TC813R-Q1 Other Parts Discussed in Thread: DP83TG721S-Q1 Tool/software: Hello Expert,
May I ask are there any methods to make DP83TG813R-Q1 enter into sleep directly after powering up?
I see the INH is output to connect EN of core power…
Hi Lijiao,
Unfortunately we currently do not have a Standard Ethernet 1Gbps device that supports 1588 Hardware Time-stamping.
We do have a Single-Pair Ethernet Device that supports 1588 Hardware Time stamping, please find link below. I have also included…
Hi Frank,
Please see our DP83TG721-Q1 which supports 1588v2. This part is very close to pin-to-pin with 720, only a few modifications are needed.
Thanks,
David
Other Parts Discussed in Thread: DP83TG720R-Q1 Hello Kallikuppa Sreenivasa.
For DP83TG720R-Q1
Will the PHY enter the sleep mode automatically when only VSLEEP Power is provided and the other Power rails are disconnected ? Your answer:
The device will be…
