Hi,
Physically, you could supply the clock to the ADC from an FPGA but I do not think you would want to. The ADS6129 is capable of a signal to noise ratio (SNR) of over 70 dBFS, depending on the frequency of the analog input. To preserve this level…
Hello Franziskus,
The clock input is referred to the DVDD supply and should be a standard CMOS level.
The clock frequency can be in the range of 0.1MHz up to 16MHz, and needs a duty cycle from 40% to 60%.
There is really no requirement on clock…
Hi Noel Fung.
Thank you for your reply.
I understood that the jitter parameter is the most effective for SNR.
Based on the results of the training video, I further increased the phase margin and loop bandwidth from 50kHz to 206kHz. In order to achieve…
Hi Adam,
We don't have an EVM for this ADC so I can't share a reference BOM. However, we do have an SNR vs Jitter excel calculator tool that can be used to show the SNR degradation when using a clock source with 100ps jitter, with a 100kHz input signal…
Hi Kobayashi-san
1) The Autosync feature is intended to synchronize the output DATA and DCLK of multiple ADCs so that the data can more easily be captured, stored and processed. Additional information on the Autosync feature is available in this document…
Karthik,
The amount of clock jitter that a system can handle is very dependent on the input frequency. For a 1 MHz input, the external clock could have close to 50 ps of jitter before the SNR degrades. For a much higher input rate, say 100 MHz, the…
How can I determine if design is stable? I have uploaded the design calc excel file in original answer, can you check? If I pull even a tiny current of 8mA, it goes into FPWM mode and the non heating IC also starts heating up.
But I would like to know…
Hi Naohiro-san,
Since the VCO frequency range has changed, I believe the wrong VCO core is loaded. After toggling the core, the tool uses the correct core for the calculation and return the original jitter and SNR.
Hi Allen, Can you go into more detail - I fully want to understand what your question is here. Bit resolution is normally associated with ADCs. Clock jitter is tied to SNR. Typically, you want the highest performance clock to achieve the best SNR & performance…
Part Number: ADC12J4000 Other Parts Discussed in Thread: ADC12J1600 , , ADC32RF45 , LMX2820 Tool/software: Hi,
we upgraded a design from ADC12J1600 to ADC12J4000 but are struggling with performance issues.Among the things changed was the clock tree…
