Hi Giora,
The oscillator and clocking path you are suggesting will not have enough jitter to "unlock" the digital serdes lanes, nor create any issues.
The oscillator you want to use, will only degrade the ADC AC performance, specifically SNR…
Hello Omer,
The ADS127l21 internal clock jitter is high enough to degrade SNR for input frequency greater than about 10Hz. If your system noise requirements can tolerate the increased noise, then you may be able to use the internal clock. The primary…
Hi Youhao,
We have modify the LM5185 transformer to 5:1 TURNS RATIO and change the Zener clamp to 8V Zener voltage,
there are no improve for the transformer whistling issue;
At present, the jitter of the switch waveform should be caused by whistling, but…
Part Number: ADS5294 Other Parts Discussed in Thread: LMK04826 I am aware of the relationship between sample clock jitter and SNR. If I am using a clock generator device, what I am unclear about is which of the jitter specifications I should be using…
Camilo,
Good afternoon! Thanks for the quick response. My principle concern is phase noise. The clock is running at 2.5 GHz. The integrated jitter is approximately 69.9 ps. Predicted close in phase noise (< 100 kHz) is quite bad and accounts > 99% of…
Part Number: PCM1794A What is the max jitter specification required on SCK3 in order to meet the specified SNR (say -125dB @ 17kHz)?
For example, with a 48kHZ sample clock (SCLK3 = 18.432MHz, 384Fs) and an output frequency we calculate the jitter needed…
Thanks once again for your help Eric,
Here's my frequency plan to see if I've understood the guidelines you've provided.
1) ADC sampling frequency. I've opted to generate this off-chip as it looks like this has a lower jitter than using the…
Hi jito,
For an oversampling ADC such as the ADS131A04, the SNR impact due to jitter is given by the equation shown below
If you want to run the ADC at 128 kSPS, the dynamic range if 85.12 dB and the OSR = 32. The 3dB BW is given by the plot shown below…
Part Number: ADS5474 Hi,
In the datasheed for ADS5474 the figure 45 shows SNR vs Input Frequency and External Clock Jitter with measurements up to 200-fs jitter.
How can user estimate SNR degradation if the jitter is up to 850-fs?
Thanks.
Hello Preethi, Can you quantify your design requirements if possible? Do you value in band or device noise floor? Do you have a certain RMS jitter requirement over a defined integration band/ You mention good phase margin margin, what is your requirement…
