• 

  Amin Eshraghi

  • 3 days ago
  • Clock & timing
  • Clock & timing forum

  RE: LMH1983: Switching between 148.5 MHz and 148.35 MHz

  Hi Darren, That is correct, PLL2 can output 148.5 MHz and PLL3 148.35 MHz. I've copied the excerpt from the datasheet below. Disabling the unused PLL will save power, which in turn will lower the devices junction temperature. So it should have...
• 

  Kazuki Itoh

  • 25 days ago
  • Clock & timing
  • Clock & timing forum

  LMH1983: PLL1 not LOCKIN

  TI Thinks Resolved

  Part Number: LMH1983 Hi team, 1080i, 59.94 Hz horizontal synchronization created from a fixed oscillator (27 MHz) is input to HIN after power up. The register settings are the device default settings. When the HIN is input, the NO_LOCK pin is supposed...
• 

  K.Shidara

  • 4 days ago
  • Clock & timing
  • Clock & timing forum

  LMH1983: Freerun clock generator etc inquiry

  Part Number: LMH1983 Hi Team Would you advise my customer's inquiry below? Please introduce any applicable clock related products. I'm thinking of making an SDI SG or Video sync signal (3 levels/BB) generator as an auxiliary equipment for...
• 

  Timothy T

  • 24 days ago
  • Clock & timing
  • Clock & timing forum

  RE: LMH1983: Register settings for Free-run and genlock

  Hello Na, The DAC voltage is a 10 bit number, so it is my expectation that programming 0 would be close to 0 V, and 1023 clost to Vdd. I was not able to confirm. Note however that the DAC output range is specified 0.5 V off the rails, so I wouldn't...
• 

  Michel Torelli1

  • 2 months ago
  • Clock & timing
  • Clock & timing forum

  RE: LMH1983: TOF2 and TOF3 randomly skipping beats when component is "hot"

  I was told by my colleagues that the same issue was present on several cameras but It might have been an unrelated issue with similar symptoms as I cannot reproduce it on more than the already defective one. Thus I suspect a bad solder joint, damaged...
• 

  Arjen de Korte

  • 3 months ago
  • Clock & timing
  • Clock & timing forum

  LMH1983: Wrong clock configuration for VCXO clock signal for PLL1

  Part Number: LMH1983 We've been using the LMH1983 for over more than a decade already to genlock our HD- and 3G-SDI cameras to an external source. Lately we have been informed by a customer that a small number of cameras show problems with PLL1 and...
• 

  james newman

  • 4 months ago
  • Clock & timing
  • Clock & timing forum

  RE: LMH1983: PLL2 at half fq on power up

  Hi Amin, yes they're all powered the same way. Unmodified the ramp rate is ~100us. When we modify the board to give a ramp rate of ~3.5ms the problem is "solved" in that it's not been seen after several thousand power cycles. A register...
• 

  Amin Eshraghi

  • 4 months ago
  • Clock & timing
  • Clock & timing forum

  RE: LMH1983: LMH1983 Configuration - User Defined Formats

  Hello, If enable auto format detect feature is enabled, then the LMH1983 will automatically detect the input Hsync timing, configure the PLL divider ratio, and lock the PLL1 to synchronize the 27MHz VCXO and 27MHz CLK output. Vsync and Hsync inputs...
• 

  Kazuki Itoh

  • 10 months ago
  • Clock & timing
  • Clock & timing forum

  LMH1983: Soft reset usage

  • Resolved

  Part Number: LMH1983 Greetings, Currently, my customer uses only the soft_reset register instead
• 

  KAEDE KUDO

  • 11 months ago
  • Interface
  • Interface forum

  LMH1983: Please tell me about 0x3A and 0x18.

  • Resolved

  Part Number: LMH1983 Hello I have a question about LMH1983 . [Q] 1. Please tell me about LVDS Boost

Didn't find what you are looking for? Post a new question.

• Ask a new question